Stacked Wafer Trench Structure for Seal Ring Crack Prevention
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Solution Overview
Problem
Existing seal ring structures in semiconductor devices are inadequate in preventing wafer cracking, especially when semiconductor wafers are stacked and bonded together, due to insufficient stress reduction and contamination prevention.
Innovation Solution
A trench structure is introduced, comprising a first trench in the first wafer and a second trench in the second wafer, both on the same side of the seal ring structure, to reduce stress and improve reliability during the sawing or cutting process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a seal ring structure is formed between scribe line and semiconductor device circuit, then wafer cracking is reduced or prevented during cutting or sawing, but the seal ring structure is insufficient to protect against wafer cracking when wafers are stacked and bonded together due to inadequate stress reduction
Solution Approach 1:
The invention divides the stress management function into multiple components: the existing seal ring structure and the newly introduced trench structure. The trench structure segments the stress path at the wafer interface, creating separate zones that can independently manage stress, thereby enhancing overall cracking prevention capability when wafers are stacked and bonded
Solution Approach 2:
The trench structure acts as an intermediary element between the seal ring structure and the wafer interface. It provides an additional layer of stress management that mediates the mechanical stresses transmitted through the bonded wafer interface, supplementing the seal ring's protective function
2Adaptability or versatility
If wafers are stacked and bonded together to form semiconductor device, then device functionality is achieved, but stress accumulation at the interface increases the likelihood of wafer cracking
Solution Approach 1:
The trench structure is formed beforehand in the wafers before stacking and bonding. It serves as a pre-prepared stress relief mechanism that cushions the interface against stress accumulation during the bonding process and subsequent device operation, preventing strength degradation at the interface
3Object-affected harmful factors
If conventional seal ring structure is used, then basic contamination prevention is provided, but contamination prevention is insufficient in the presence of stacked wafers
Solution Approach 1:
The trench structure segments the potential contamination pathways that exist in conventional seal ring designs. By creating physical barriers through the trenches, the invention divides and isolates contamination risks, making it more difficult for contaminants to reach sensitive areas of the stacked semiconductor device
Data Source
AI summary
A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.