Stacked Wafer Alignment Using Non-Metallic Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor wafer alignment processes struggle to achieve the alignment accuracy required for feedback/feedforward wafer processing methodologies due to the inability to use registration marks before stacking, especially with the trend towards smaller devices and larger wafers, leading to reduced alignment margins.
Innovation Solution
The use of non-metallic vias in semiconductor wafers allows features or marks on a second stacking wafer to be viewed through these vias, enabling in situ alignment during the stacking process, thus allowing registration marks to be used prior to stacking and bonding, facilitating feedback/feedforward processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional wafer alignment process is used, then alignment can be performed, but alignment accuracy is insufficient for feedback/feedforward methodologies
Solution Approach 1:
The patent divides the wafer structure into segments by creating through-vias that expose registration marks on underlying wafers. This segmentation allows the registration marks to be visible and accessible for alignment purposes without requiring complex disassembly or angle-based viewing methods.
Solution Approach 2:
The through-vias act as intermediaries that transmit visual information from registration marks on lower wafers to the alignment system. These via structures serve as optical pathways that enable direct viewing of registration marks without requiring complex optical systems or angle-based viewing.
2Productivity
If larger wafers are used to yield more devices, then productivity increases, but alignment margin decreases
Solution Approach 1:
The patent transitions from planar alignment methods to a three-dimensional approach by creating through-vias that extend vertically through the wafer stack. This dimensional change allows registration marks to be accessed from the top surface through the via structures, enabling precise alignment on larger wafers where traditional margin-based alignment becomes insufficient.
3Extent of automation
If registration marks are not visible before stacking, then alignment cannot be performed with feedback methodologies, but viewing through films at an angle is required
Solution Approach 1:
The registration marks are prepared and positioned on the wafers before stacking, and through-vias are created to expose them. This preliminary preparation enables feedback methodologies to be used during the stacking process itself, rather than requiring complex angle-based viewing or post-stack alignment adjustments.
Data Source
AI summary
A semiconductor device assembly including a first semiconductor wafer having a first side and a second side opposite the first side, the first semiconductor wafer including: a first plurality of semiconductor devices at the first side, a plurality of non-metallic vias extending from the second side towards the first side, and a plurality of alignment marks, each vertically aligned with a corresponding one or more of the plurality of non-metallic vias, a second semiconductor wafer including a second plurality of semiconductor devices and a plurality of registration marks, each of the plurality of registration marks vertically aligned with a corresponding one or more of the plurality of alignment marks.