Stacked Wire Structure for Semiconductor Device Density
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving higher device density, performance, and lower costs as they transition to nanometer technology process nodes, particularly in forming effective three-dimensional designs that prevent short-circuiting and enhance carrier mobility.
Innovation Solution
A method for forming a semiconductor device structure involving a stacked wire structure, where alternating semiconductor layers are formed over a substrate with specific surface orientations, followed by the creation of fin structures, source/drain structures with rounded corners, and a metal gate structure, which improves surface area contact and reduces the risk of short-circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar semiconductor devices are used, then manufacturing is simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) device architecture to a three-dimensional stacked wire structure. Multiple wire structures are formed at different vertical levels above the substrate, enabling higher device density by utilizing the vertical dimension for routing and interconnects, thereby resolving the contradiction between maintaining manufacturing simplicity and achieving higher device density.
2Productivity
If device dimensions are reduced to nanometer nodes, then device density increases, but short-circuiting risk increases
Solution Approach 1:
By forming wire structures at multiple vertical levels separated by dielectric layers, the patent increases the physical separation between conductive paths. This vertical stacking approach reduces the risk of short-circuiting between adjacent wires while maintaining high device density, as the dielectric layers provide electrical isolation between stacked wires at different levels.
Solution Approach 2:
The patent implements a nested structure where wire structures are stacked vertically with dielectric layers between them, creating a multi-level interconnect architecture. Each wire structure is nested within its own dielectric enclosure, providing electrical isolation and preventing short-circuits while maximizing space utilization for higher device density.
3Reliability
If conventional contact structures are used, then manufacturing is simpler, but carrier mobility is limited
Solution Approach 1:
The patent forms contact structures with rounded corners instead of sharp直角, which reduces stress concentration and improves carrier mobility at the contact interfaces. The curved geometry of the contact structures modifies the electric field distribution and reduces scattering effects, thereby enhancing carrier transport while the overall device structure remains manageable.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.