Stacked Semiconductor Wiring Structure for Warpage Reduction
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Solution Overview
Problem
The increasing number of input/output (I/O) connections in semiconductor chips leads to larger and thicker semiconductor substrates, resulting in decreased yield and warpage issues, which are not effectively addressed by existing manufacturing processes.
Innovation Solution
A wiring structure comprising an upper conductive structure, a lower conductive structure, and an intermediate layer that bonds them together, with high-density circuit layers and reduced dielectric layer thickness, allowing for efficient electrical connection and singulation to improve yield and reduce warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of I/O connections is increased, then the electrical performance and functions are improved, but the substrate thickness and warpage increase
Solution Approach 1:
The substrate is divided into multiple separate substrates that are stacked and bonded together through an intermediate layer. This segmentation allows the I/O connections to be distributed across multiple thinner layers rather than concentrated in a single thick substrate, thereby increasing the number of I/O connections while keeping each individual substrate thin and reducing overall warpage.
2Adaptability or versatility
If the number of I/O connections is increased, then the electrical performance and functions are improved, but the substrate warpage increases
Solution Approach 1:
By segmenting the substrate into multiple thin layers stacked together, the structural stability of each individual layer is maintained, preventing warpage. The intermediate layer bonds these stable thin layers together to form a composite structure that can accommodate high I/O connections without experiencing the warpage issues of a single thick substrate.
Solution Approach 2:
The patent creates a composite substrate structure by bonding multiple separate substrates together through an intermediate layer. This composite construction combines the advantages of multiple thin, stable layers while achieving the functional requirements of high I/O connections, effectively reducing warpage compared to a monolithic thick substrate.
3Adaptability or versatility
If the substrate size is increased to accommodate more I/O connections, then the electrical performance is improved, but the manufacturing yield decreases
Solution Approach 1:
Instead of manufacturing a single large substrate that would have low yield, the patent segments the system into multiple smaller substrates that can be manufactured with higher yield. These smaller substrates are then stacked and bonded together to achieve the equivalent functionality of a large substrate, thereby maintaining high manufacturing yield while accommodating high I/O connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves a compromise between manufacturing cost and yield, enabling the production of semiconductor packages with high I/O counts while minimizing substrate thickness and warpage, thereby improving overall manufacturing efficiency.
Implementation Method 1
an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together
Data Source
AI summary
A wiring structure includes an upper conductive structure, a lower conductive structure, a lower encapsulant and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The lower encapsulant surrounds a lateral peripheral surface of the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.


