Stacked Wiring Resin Structure to Reduce WLP Warpage
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Solution Overview
Problem
The existing Wafer Level Package (WLP) manufacturing process faces issues with wafer warpage due to thermal expansion coefficient differences, leading to vacuum suction errors and difficulties in wiring formation, especially when stacking multiple layers, and the process is costly due to time-consuming resin molding steps.
Innovation Solution
The semiconductor device features a first and second wiring layer with semiconductor chips mounted on each, through-holes for integral molding resin layers, and through electrodes connecting the layers, allowing for reduced manufacturing costs by eliminating the need for multiple resin molding steps and addressing warpage issues through strategic substrate handling and peeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate resin molding steps are performed for each wiring layer, then each layer can be individually sealed, but manufacturing time and cost increase significantly
Solution Approach 1:
The patent merges multiple separate resin molding steps into a single integrated molding process. The molding resin is applied to cover multiple wiring layers simultaneously, and all layers are sealed in one curing cycle, eliminating the need for repeated molding operations while maintaining adequate sealing quality for each layer.
Solution Approach 2:
The patent performs preliminary stacking of multiple wiring layers before the final resin molding step. By preparing the layered structure in advance and then applying the molding resin once to seal all layers together, the process avoids time-consuming sequential molding while ensuring proper sealing.
2Reliability
If wafer is sealed with molding resin in conventional WLP process, then chips are protected, but wafer warpage occurs due to thermal expansion coefficient difference
Solution Approach 1:
The patent segments the wafer into multiple thinner wiring layers rather than treating it as a single thick wafer. This segmentation reduces the overall thickness and minimizes thermal expansion differences, thereby reducing warpage while still providing chip protection through the molding resin.
Solution Approach 2:
The patent changes the physical parameters of the structure by reducing wafer thickness through multi-layer segmentation. This parameter change reduces the thermal mass and thermal expansion coefficient difference, thereby minimizing warpage during the molding process while maintaining chip protection.
3Ease of manufacture
If warped wafer is fixed in semiconductor process device, then molding can be performed, but vacuum suction error occurs making wiring formation difficult
Solution Approach 1:
The patent performs preliminary stacking and positioning of wiring layers before the molding step. By preparing the layered structure in advance on a stable substrate, the layers are pre-aligned and stabilized, preventing warpage-related positioning errors during subsequent wiring formation processes.
Solution Approach 2:
The patent uses a substrate as an intermediary medium to support the wiring layers during manufacturing. The substrate provides a stable platform that prevents warpage and ensures proper alignment, allowing both molding and precise wiring formation to be performed accurately.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and improves yield by integrating molding resin layers across stacked wiring layers, minimizing defects and wafer warpage-related issues, while maintaining a thin package structure without substrates.
Implementation Method 1
a first molding resin layer 104a covering the first semiconductor chip 102a and a second molding resin layer 104b covering the second semiconductor chip 102b are integrally formed through the through-hole 111
Implementation Method 2
a through electrode 110 that penetrates the first molding resin layer 104a and connects the first wiring 121a and the second wiring 121b to each other
Data Source
AI summary
A semiconductor device includes a first wiring layer, a first semiconductor chip, a second wiring layer, and a second semiconductor chip. In addition, in the semiconductor device, a molding resin layer that molds the first semiconductor chip on the first wiring layer and a molding resin layer that molds the second semiconductor chip on the second wiring layer are formed, and the molding resin layers are integrally formed through a through-hole.