Vertical Channel Memory Cell Structure for Lower-Cost Integration
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Solution Overview
Problem
The increased integration of semiconductor memory devices leads to higher manufacturing costs due to the use of advanced process equipment, and existing semiconductor devices face challenges in optimizing performance and resistance properties.
Innovation Solution
The implementation of vertical channel transistors in semiconductor devices, which include specific configurations of bit lines, word lines, and semiconductor patterns, allows for improved integration and reduced manufacturing costs while enhancing resistance and current driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If increased integration of semiconductor memory devices is implemented, then device integration is improved, but manufacturing costs increase due to advanced process equipment requirements
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, utilizing the third dimension (vertical direction) to increase device integration. The vertical channel extends perpendicular to the substrate surface, allowing multiple devices to be stacked in the vertical direction, thereby improving integration without requiring proportionally more expensive advanced planar process equipment
2Reliability
If conventional planar transistors are used, then manufacturing is simpler, but resistance properties and current driving capability are insufficient
Solution Approach 1:
The patent employs vertical channel transistors where the channel extends in the vertical direction perpendicular to the substrate, increasing the effective channel length without proportionally increasing the planar footprint. This three-dimensional structure improves resistance properties and current driving capability while the gate electrode wraps around the channel to provide enhanced control
Solution Approach 2:
The gate electrode is configured to wrap around or envelop the vertical channel, creating a nested structure where the gate surrounds the channel in multiple directions. This nested configuration provides superior electrostatic control and threshold voltage adjustment capability compared to conventional planar gates
Data Source
AI summary
Some example embodiments are directed to semiconductor device that includes a first bit line extending in a first direction, a first semiconductor pattern on the first bit line and including vertical portions and a horizontal portion, first word lines spaced apart from each other in the first direction on the horizontal portion and extending in a second direction, second bit lines spaced apart from each other in the first direction and on the first word lines and extending in the second direction, a gate insulating pattern between the vertical portions of the first semiconductor pattern and the first word lines and extending between the vertical portions and the second bit lines, a second semiconductor pattern on the second bit lines, and a second word line extending in the first direction on the second semiconductor pattern. The first word lines and the second bit lines vertically overlap each other.