Stacking Cabled I/O Slots Signal Integrity

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Solution Overview

Problem

Existing computing device I/O slots face challenges with signal propagation delays and electrical interference when routing high-speed data signals, and the provision of power over flexible cables increases the risk of short-circuiting and complexity.

Innovation Solution

The implementation of stacking cabled I/O slots that use a daisy-chained arrangement with slot allocation and population logic to establish high-speed data connections via cables while keeping power and logic signals separate from data signals, reducing the need for re-timers and minimizing interference risks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If high-speed data signals are routed through flexible cables with power, then I/O devices can be connected remotely, but signal propagation delays and electrical interference increase

Engineering Contradiction:
ImproveI/O device connectivityVSAvoidsignal propagation delays and electrical interference
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The I/O slot is divided into separate functional components: a first connector for power and logic signals, and a second connector for high-speed data signals. This segmentation allows power and data pathways to be physically separated, reducing electrical interference and propagation delays while maintaining flexible cable connectivity.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If power and logic signals are combined with data signals in the same cable, then cable connections are simplified, but electrical interference and short-circuiting risks increase

Engineering Contradiction:
Improvecable connection structureVSAvoidelectrical interference and short-circuiting risks
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The connector is segmented into two separate connectors: a first connector that receives power and logic signals, and a second connector that receives high-speed data signals. This physical separation eliminates electrical interference between power and data signals while maintaining organized cable management through the daisy-chained connector architecture.

Inventive Principle:
Principle #1Segmentation

3Productivity

If re-timers are added to compensate for signal propagation delays, then data throughput performance can be maintained, but device complexity and interference risks increase

Engineering Contradiction:
Improvedata throughput performanceVSAvoidre-timer circuitry and interference risks
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the high-speed data signal pathway from the power and logic signal pathways, providing a dedicated separate connector for data signals. This eliminates the need for re-timer circuitry by ensuring clean, interference-free signal transmission through dedicated data-only cable connections.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10957999B1Stacking cabled input/output slots
Publication Date: 2021.03.23 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10957999B1 patent drawing
  • US10957999B1 patent drawing
  • US10957999B1 patent drawing

AI summary

One or more stacking cabled I/O slots may be installed in a stacked arrangement on a computing device, such as in an I/O expansion socket of a computing device motherboard. Slot detection and population logic associated with each of the one or more stacking cabled I/O slots enables signaling from each installed stacking cabled I/O slot, in order for its presence and location relative to any other installed stacking cabled I/O slot to be identified to and recognized by the computing device. High speed data signals through an installed stacking cabled I/O slot are coupled to the computing device via a cable, while power and logic signals are exchanged between the computing device and the one or more stacking cabled I/O slots via connections to the I/O expansion socket.