Nanosheet Source/Drain Structure With Stacking Faults for Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling and improving current control while effectively suppressing short channel effects, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates a specific design featuring active patterns with lower and sheet patterns, gate structures, source/drain recesses, and source/drain patterns that include stacking faults, which enhance channel control and mobility by strategically arranging and spacing these elements to manage channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistor with three-dimensional channel is used, then current control ability is improved, but manufacturing complexity increases
Solution Approach 1:
The active pattern is segmented into multiple sheet patterns (first sheet pattern, second sheet pattern, etc.) spaced apart in the first direction, with gate structures positioned between them. This segmentation enables multi-gate control capability while maintaining a manufacturable structure by dividing the complex three-dimensional channel into manageable planar components.
Solution Approach 2:
The invention transitions from conventional planar transistors to a multi-gate structure where gate electrodes are positioned in multiple locations (between sheet patterns and overlying them) to provide control from multiple dimensions. This dimensional approach improves current control ability by enabling electrostatic control from multiple directions without requiring fully complex three-dimensional fabrication.
2Productivity
If device scaling is performed, then density is increased, but short channel effect worsens
Solution Approach 1:
The channel region is divided into multiple sheet patterns with gate structures positioned between them. This segmentation allows for shorter channel lengths (enabling higher density) while maintaining multiple gate control points that suppress short channel effects by providing better electrostatic control over the channel potential.
Solution Approach 2:
Gate structures serve as intermediary elements positioned between the source/drain regions and the channel. By placing gate structures in multiple locations (between sheet patterns and overlying them), the invention provides intermediate control points that regulate channel potential and suppress short channel effects even at scaled dimensions.
3Reliability
If stacking fault is introduced in source/drain pattern, then charge carrier mobility is improved, but structural complexity increases
Solution Approach 1:
Stacking faults are introduced locally within specific regions of the source/drain patterns rather than throughout the entire device. This localized approach improves charge carrier mobility in critical regions (such as near the channel interface) while minimizing the overall structural complexity and maintaining manufacturability.
Solution Approach 2:
The invention utilizes stacking faults as a parameter change in the crystal structure of the source/drain patterns. By controlling the presence and orientation of stacking faults, the material properties (specifically charge carrier mobility) are modified without fundamentally changing the overall device architecture or fabrication process complexity.
Data Source
AI summary
A semiconductor device includes an active pattern having a lower pattern, and a plurality of sheet patterns spaced apart from the lower pattern in a first direction; first and second structures disposed on the lower pattern, wherein the first and second structures are arranged and spaced apart from each other in a second direction; a source/drain recess defined between first and second gate structures; and a source/drain pattern filling the source/drain recess, wherein the source/drain pattern includes a stacking fault spaced apart from the lower pattern.