Stage-Based Spice Deck for Path Analysis
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Solution Overview
Problem
Current electronic design automation (EDA) tools face inefficiencies in static timing analysis, including repeated iterative processes, divergent timing analysis between signoff and physical implementation, pessimistic timing characteristics, high resource requirements, and excessive turnaround time, which hinder cost minimization, time-to-market, and performance optimization in electronic circuit design.
Innovation Solution
A computer-implemented method and system for performing Path-Based Analysis (PBA) using a stage-based approach, which involves creating a SPICE deck by initiating PBA for an electronic circuit design, identifying stages, performing delay calculations, generating stage spice decks, and connecting them to form a complete path spice deck, utilizing information from standard parasitic exchange format, Verilog, and design constraint files.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional static timing analysis is used, then timing analysis can be performed, but false-positive violations increase and accuracy decreases
Solution Approach 1:
The patent segments the timing analysis into distinct stages (launch stage, capture stage, and path stage) with different SPICE deck configurations. Each stage is analyzed independently with optimized parameters, allowing for more precise measurement without the false positives that occur in traditional unified analysis approaches.
Solution Approach 2:
The patent applies local quality by using different SPICE deck configurations and analysis parameters for different stages of the timing path. The launch stage uses one configuration, the capture stage uses another, and the path stage uses a third, allowing each local region to be analyzed with the most appropriate parameters for that specific stage.
2Reliability
If repeated iterative processes are used between timing signoff and physical implementation, then timing analysis can be performed, but turnaround time increases and productivity decreases
Solution Approach 1:
The patent performs preliminary actions by pre-configuring multiple SPICE deck templates for different stages before the actual timing analysis. The launch stage SPICE deck, capture stage SPICE deck, and path stage SPICE deck are all prepared in advance with appropriate parameters, eliminating the need for repeated iterative configurations and significantly reducing turnaround time.
3Measurement precision
If comprehensive timing analysis is performed, then timing characteristics can be assessed, but resource requirements and device complexity increase
Solution Approach 1:
The patent segments the comprehensive timing analysis into three distinct stages, each with its own SPICE deck configuration. This segmentation allows the complex analysis to be broken down into manageable parts that can be processed independently, reducing the peak memory and processing requirements compared to performing a single comprehensive analysis.
Solution Approach 2:
The patent applies local quality by optimizing each stage's SPICE deck configuration for its specific requirements. The launch stage uses parameters optimized for launch conditions, the capture stage uses parameters optimized for capture conditions, and the path stage uses parameters optimized for path delay calculation. This localized optimization reduces overall computational complexity while maintaining comprehensive analysis accuracy.
Data Source
AI summary
The present disclosure relates to a system and method for performing Path-Based Analysis (PBA) of an electronic circuit design. Embodiments may include receiving a command to create a spice deck of a timing path associated with the electronic circuit design. In response to receiving the command, embodiments may further include initiating PBA for the timing path and identifying one or more stages within the timing path. Embodiments may also include performing a delay calculation for each of the one or more stages and generating a stage spice deck for each of the one or more stages based upon, at least in part, information from the delay calculation, wherein the stage spice deck encapsulates all elements of the stage. Embodiments may further include connecting the stage spice deck for each of the one or more stages in series to form a complete path spice deck.