Stage Circuit Voltage Control for Uniform Display Luminance
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Solution Overview
Problem
Existing display devices experience luminance differences across horizontal lines due to variations in scan signal distribution, which affect display quality.
Innovation Solution
A stage circuit design that includes a controller, driver, connection portions, and a reset to manage voltage levels and electrical connections between nodes, using multiple power inputs to minimize luminance disparities by controlling scan clock signals and enabling precise signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If scan signals are distributed across horizontal lines using conventional stage circuits, then scan driving function is achieved, but luminance differences occur across horizontal lines
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting voltage levels (using first power VDD and second power VDD/2) and timing parameters (phase shifting between first and second scan signals) to compensate for luminance differences across horizontal lines, achieving uniform display quality
Solution Approach 2:
The patent implements local quality by providing different voltage levels and signal phases to different horizontal line groups (first horizontal lines vs. second horizontal lines), allowing each region to be optimized independently for uniform luminance output
2Illumination intensity
If multiple power inputs are used to control voltage levels, then luminance differences are reduced, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the stage circuit to perform multiple functions using shared components: the same circuit structure handles both voltage control and timing control, and the phase shifting mechanism serves both signal generation and synchronization purposes, reducing overall complexity
Data Source
AI summary
A stage circuit includes a controller connected to first and second powers, and configured to control a voltage of a connection control line in response to carry signals of first and second carry input terminals, a driver connected to the first power and to a third power, and configured to control voltages of first and second nodes, first outputs configured to receive one of scan clock signals or output enable scan signals based on a voltage of one of local nodes, connection portions configured to control an electrical connection between the local nodes and the first node in response to the voltage of the connection control line, and a reset connected between the connection control line and a fourth power, and configured to control an electrical connection between the connection control line and the fourth power based on the voltage of the second node.