Stage Circuit and Scan Driver for Display Panels
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Solution Overview
Problem
Existing display devices face challenges in minimizing the mounting area of stages in scan drivers, which affects the reliability and efficiency of scan signal transmission and increases stress on transistors.
Innovation Solution
A stage circuit and scan driver design that includes an output part, a controller, a pull-up part, and a pull-down part with capacitors and transistors, which control node voltages based on carry signals and clock signals to enhance falling times and reduce voltage rise, thereby minimizing transistor mounting area and stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stages are mounted on panels, then scan signals can be supplied to scan lines, but mounting area is occupied
Solution Approach 1:
The patent merges the stage circuit with the pixel structure by integrating scan signal generation directly into the pixel array. The stage circuit includes transistors and capacitors that are formed in the same pixel region, eliminating the need for separate mounting areas while maintaining scan signal transmission functionality.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking transistor layers and capacitor structures within the pixel depth. Multiple transistor gates and capacitor electrodes are arranged in different layers, allowing the stage circuit to occupy minimal planar area while maintaining full functionality through three-dimensional structural integration.
2Area of stationary object
If transistor size is reduced to minimize mounting area, then mounting area decreases, but stress on transistors increases
Solution Approach 1:
The patent applies different structural qualities to different parts of the transistor. The channel region uses optimized material composition and thickness, while the source and drain regions use different doping profiles. This local optimization allows smaller transistor dimensions while maintaining stress tolerance through region-specific property enhancement.
Solution Approach 2:
The patent employs composite material structures in the transistor, combining multiple semiconductor layers with different mechanical and electrical properties. The stacked transistor structure uses varying material compositions in different layers to distribute and reduce stress while maintaining electrical performance in miniaturized devices.
3Area of stationary object
If voltage rise is reduced to minimize transistor area, then mounting area decreases, but falling time of node voltages decreases
Solution Approach 1:
The patent uses pre-charged capacitors and pre-biased transistor gates to prepare the circuit state before signal transitions. The capacitor is pre-charged to a specific voltage level, and transistor gates are pre-biased to optimal operating points, enabling faster voltage transitions without requiring larger device areas.
Solution Approach 2:
The patent employs periodic clock signals to drive the stage circuit operations. The regular periodic timing allows optimized transistor switching cycles where voltage rise and fall occur during specific phases, enabling area-efficient design while maintaining adequate transition times through synchronized periodic operation.
Data Source
AI summary
A stage circuit includes an output part configured to supply a carry signal to a first output terminal and a scan signal to a second output terminal, in response to a voltage of a first node, a voltage of a second node, and a first clock signal being supplied to a first input terminal, a controller configured to control the voltage of the second node in response to the first clock signal being supplied to the first input terminal, a pull-up part configured to control the voltage of the first node in response to a carry signal of a previous stage being supplied to a second input terminal, and a pull-down part configured to control the voltage of the first node in response to the voltage of the second node and the carry signal of a next stage being supplied to a third input terminal.