Stage Circuit Scan Driver Leakage Current Control

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Solution Overview

Problem

Existing display devices, particularly organic light-emitting display devices, face challenges in efficiently supplying scan signals to pixels due to leakage current issues, which affect the accuracy and stability of luminance emission.

Innovation Solution

A stage circuit configuration using P-type or N-type transistors to supply high-level or low-level scan signals, respectively, is implemented, incorporating specific transistor and capacitor arrangements to control node voltages and clock signals, ensuring stable scan signal delivery to scan lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional stage circuits are used to supply scan signals, then the basic scan signal transmission function is achieved, but leakage current occurs affecting luminance accuracy and stability

Engineering Contradiction:
Improvescan signal supply stabilityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The stage circuit is divided into multiple functional blocks: input circuit for clock signal input, output circuit for scan signal output, first driver circuit for node voltage control, second driver circuit for power supply control, and third driver circuit for additional node control. This segmentation allows each block to address specific leakage issues independently, improving overall reliability while managing harmful leakage current through targeted circuit design in each segment.

Inventive Principle:
Principle #1Segmentation

2Illumination intensity

If P-type transistors are used to supply high-level scan signals, then high-level signal delivery is achieved, but leakage current control becomes more difficult

Engineering Contradiction:
Improvescan signal levelVSAvoidleakage current control
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The driver circuits incorporate feedback mechanisms where the output of each driver circuit is fed back to control subsequent circuit states. The first driver circuit controls node voltages based on feedback from the input circuit, the second driver circuit adjusts power supply based on feedback from node voltages, and the third driver circuit provides additional feedback control. This feedback system enables precise control of P-type transistor operation to maintain high-level scan signals while suppressing leakage current through continuous monitoring and adjustment.

Inventive Principle:
Principle #23Feedback

3Illumination intensity

If N-type transistors are used to supply low-level scan signals, then low-level signal delivery is achieved, but voltage control precision is reduced

Engineering Contradiction:
Improvescan signal levelVSAvoidvoltage control accuracy
Core Design Contradiction:
Illumination intensityVSMeasurement precision

Solution Approach 1:

The circuit dynamically changes operating parameters including voltage levels, current thresholds, and timing parameters based on feedback signals. The driver circuits adjust their operating points in real-time, modifying voltage control parameters to maintain precision despite using N-type transistors. By changing parameters such as gate voltages, drain currents, and timing sequences, the system achieves accurate low-level scan signal delivery while maintaining voltage control precision through adaptive parameter adjustment.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10706784B2Stage circuit and scan driver using the same
Publication Date: 2020.07.07 SAMSUNG DISPLAY CO LTD
  • US10706784B2 patent drawing
  • US10706784B2 patent drawing
  • US10706784B2 patent drawing

AI summary

A stage circuit includes an output circuit configured to supply, to a first output terminal, a first clock signal supplied to a second input terminal or to supply a voltage of a second power source supplied to a second power input terminal, in response to voltages of a first node and a second node, an input circuit configured to control voltages of a third node and a fourth node in response to a shift pulse or a gate start pulse supplied to a first input terminal, a third clock signal supplied to a third input terminal, and a fourth clock signal supplied to a fourth input terminal, and a first driver configured to control the voltages of the first and second nodes in response to both the third clock signal and the voltages of the third and fourth nodes.