Stage Circuit Scan Driver Merging High Low Signals
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Solution Overview
Problem
Current display devices face challenges in efficiently generating and managing scan signals for pixels, particularly in minimizing leakage current and optimizing the configuration of scan drivers to reduce complexity and cost while maintaining reliability.
Innovation Solution
The proposed solution involves a stage circuit configuration that includes two sub-stage circuits, each receiving specific clock signals and power supplies to control node voltages and generate scan signals with distinct pulse levels, allowing for the integration of scan drivers into a single shift register configuration, thereby simplifying the scan driver architecture and reducing dead space in the display device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate scan drivers are used for high level and low level scan signals, then signal generation reliability is improved, but device complexity and dead space increase
Solution Approach 1:
The patent combines the functions of generating high level scan signals and low level scan signals into a single scan driver circuit. The scan driver includes a first sub-stage circuit that generates high level scan signals and a second sub-stage circuit that generates low level scan signals, both integrated within the same driver structure, thereby reducing device complexity and dead space while maintaining the reliability of separate signal generation paths
Solution Approach 2:
The scan driver is segmented into functional sub-stages: a first sub-stage circuit for generating high level scan signals and a second sub-stage circuit for generating low level scan signals. This segmentation allows each sub-stage to be optimized for its specific function while being integrated into a unified driver structure, resolving the contradiction between reliability and complexity
2Object-generated harmful factors
If complex scan driver configuration is used to minimize leakage current, then leakage current reduction is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent utilizes parameter changes in transistor operation by switching between N-type and P-type transistors in different sub-stage circuits. The first sub-stage circuit uses N-type transistors for high level signal generation while the second sub-stage circuit uses P-type transistors for low level signal generation, optimizing leakage current characteristics through parameter variation without requiring overly complex circuit configurations
Solution Approach 2:
The scan driver is designed as a universal circuit that can generate both high level and low level scan signals using a unified architecture. The circuit employs clock signals and power supply voltages that can be adjusted to optimize performance for different signal levels, providing multi-functionality that reduces manufacturing complexity while maintaining effective leakage current minimization
Data Source
AI summary
A stage circuit including: a first sub-stage circuit coupled to a first input terminal receiving an input signal, a second input terminal receiving a first clock signal, and a third input terminal receiving a second clock signal, the first sub-stage circuit controlling a voltage of a first node, a second node, and a third node based on the input signal and the first and second clock signals, and supplying a first scan signal to a first output terminal based on the voltage of the second and third nodes; and a second sub-stage circuit coupled to the second input terminal, a fourth input terminal receiving a third clock signal, and the first and second nodes, the second sub-stage circuit supplying a second scan signal to a second output terminal based on the first and third clock signal, and the voltage of the first and second nodes.