Stage Circuit Minimizing Dead Space via Segmented Transistor Control

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Solution Overview

Problem

Existing stage circuits in display devices face challenges in securing reliability while minimizing dead space, particularly in achieving high mobility and reliability in scan signal generation.

Innovation Solution

The stage circuit incorporates a gate sync transistor for high mobility and source sync or single gate transistors for reliability, utilizing a specific configuration of transistors and capacitors to control voltage nodes and electrical connections in response to clock and carry signals, ensuring efficient scan signal generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If a stage circuit uses conventional transistor configurations, then the circuit can generate scan signals, but the circuit occupies excessive dead space and achieves low mobility

Engineering Contradiction:
Improvedead spaceVSAvoidmobility
Core Design Contradiction:
Area of moving objectVSProductivity

Solution Approach 1:

The stage circuit is divided into multiple functional units: input unit, output units, control units, and driving units. Each unit performs a specific function in the scan signal generation process, allowing for optimized space utilization and improved mobility through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a back-gate electrode dimension for transistors, allowing voltage control from a new spatial dimension. This enables precise control of transistor switching behavior, improving mobility while minimizing the area occupied by conventional gate structures

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the stage circuit uses N-type transistors only, then the circuit structure is simplified, but the reliability of scan signal generation is compromised

Engineering Contradiction:
ImprovereliabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Different transistor types are selectively applied to different parts of the circuit based on local requirements. N-type transistors are used where high mobility is needed, while P-type transistors are used where reliability and signal stabilization are critical, creating a heterogeneous but optimized circuit architecture

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Control units with multiple transistors act as intermediaries between signal input and output, coordinating the operation of different transistor types. These control units manage the interaction between N-type and P-type transistors to ensure reliable scan signal generation while maintaining circuit functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If the stage circuit generates scan signals efficiently, then productivity is improved, but dead space increases

Engineering Contradiction:
ImprovemobilityVSAvoiddead space
Core Design Contradiction:
ProductivityVSArea of moving object

Solution Approach 1:

The circuit uses dynamic voltage control through back-gate electrodes and multiple control units that adjust transistor operating states in real-time. This dynamic control optimizes signal propagation speed and efficiency while maintaining compact circuit dimensions through adaptive switching behavior

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12154637B2Stage circuit
Publication Date: 2024.11.26 SAMSUNG DISPLAY CO LTD
  • US12154637B2 patent drawing
  • US12154637B2 patent drawing
  • US12154637B2 patent drawing

AI summary

A stage circuit includes an input unit connected to a first input terminal receiving a gate start pulse or a previous stage carry signal to control a voltage of a first node, a first output unit connected to a fourth input terminal to which a clock signal is input and supplying a scan signal to a first output terminal corresponding to a voltage of the first node and a second node, a second output unit connected to a third input terminal to which a second carry clock signal is input and supplying a carry signal to a second output terminal corresponding to the voltage of the first node and the second node, a first control unit connected to a first power input terminal to which first power is input and controlling a voltage of a third node, and a second control unit connected to a second power input terminal.