3D-Stacked Image Sensor Readout With Staged ADC Sub-Columns
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Solution Overview
Problem
3D-stacked image sensors face challenges with rolling shutter discontinuity and digital data transmission issues due to sub-column parallel readout architectures, which affect image quality and frame rate, especially when windowing is applied.
Innovation Solution
The proposed solution involves a stack with a pixel array tier and a control logic tier where each sub-column is electrically connected to a dedicated stage in the control logic tier, allowing for sequential readout and interconnection of analog-to-digital converters in series, performing coarse and finer conversions to reduce rolling shutter discontinuity and improve frame rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sub-column parallel readout architecture is used, then frame rate is improved, but rolling shutter discontinuity occurs
Solution Approach 1:
The pixel array is divided into multiple sub-columns, each with its own dedicated ADC stage. This segmentation allows parallel readout of multiple sub-columns simultaneously, improving frame rate while maintaining continuous scanning within each sub-column to eliminate rolling shutter discontinuity.
Solution Approach 2:
The patent introduces a temporal dimension to the readout process by sequentially activating different sub-columns across multiple frames. This allows the system to achieve high parallelism through multi-frame accumulation rather than simultaneous single-frame readout, resolving the contradiction between speed and image continuity.
2Productivity
If sub-column parallel readout architecture is used, then parallelism is improved, but digital data transmission difficulty increases
Solution Approach 1:
The ADC functionality is segmented into multiple dedicated stages, one for each sub-column. This segmentation distributes the conversion load across multiple independent units, enabling parallel operation while simplifying data transmission since each stage handles only its assigned sub-column's data independently.
Solution Approach 2:
Each dedicated ADC stage acts as an intermediary between its corresponding sub-column and the output interface. This intermediary approach allows parallel conversion operations while managing data transmission through standardized, simplified interfaces for each stage, reducing overall system complexity.
3Productivity
If windowing is applied to increase frame rate, then productivity is improved, but number of ADCs is reduced which is not desirable
Solution Approach 1:
Each dedicated ADC stage is designed to be universally applicable to any sub-column. The stages can be dynamically activated or deactivated based on windowing requirements, allowing the same hardware resources to serve multiple functions: full-array readout when needed, or selective sub-column readout during windowing operations, maintaining ADC quantity while improving frame rate.
Solution Approach 2:
The system dynamically configures which ADC stages are active based on the readout mode. During windowing operations, only the necessary stages are activated, effectively reducing the operational ADC count to match the reduced pixel array, thereby maintaining frame rate improvements without permanently reducing the ADC infrastructure.
Data Source
AI summary
An image sensor is proposed to have a stack with at least a pixel array tier and a control logic tier. The pixel array tier comprises an array of pixels which are arranged into pixel columns n, each pixel column n comprising a number of N sub-columns: Each sub-column is denoted by N(n,i) with 1≤i≤N. The control logic tier comprises an array of analog-to-digital-converters which are arranged into ADC columns m, wherein each analog-to-digital converter comprises a number of M stages. Each stage is denoted by M(m,j) with 1≤j≤M, Furthermore, each respective sub-column N(n,i) is electrically connected to a dedicated stage M(m,j=i) and the stages M(m,j) are electrically interconnected to form the analog-to-digital converters, respectively. The control logic tier is arranged to sequentially read out the sub-columns N(n,i), wherein the stages M(m,j=i) dedicated to the sub-columns N(n,i) are arranged as input stages to sequentially receive signal levels of the pixels in the sub-columns N(n,i), respectively. The input stages are arranged to perform on the sequentially received signal levels a coarse first analog-to-digital conversion. The remaining stages M(m,j≠i) are arranged to sequentially perform finer analog-to-digital conversions of the received signal levels.