Staged Buffer Caching for Automated Test Equipment Memory Complexity
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Solution Overview
Problem
Conventional automated test equipment (ATE) systems for non-algorithmic components and devices require expensive and complex interleaved dynamic random access memories (DRAMs) for high-speed read/write operations, which is costly and inefficient.
Innovation Solution
A system utilizing staged buffer caching with a test controller containing non-interleaved DRAM, where portions of random test data are selectively transferred from a buffer memory to a cache within a bridge circuit and then to a functional unit, eliminating the need for a large interleaved DRAM unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interleaved DRAM is used for high-speed read/write operations in conventional ATE systems, then testing performance is improved, but system cost and complexity increase
Solution Approach 1:
The patent divides the buffer memory system into three separate memory units of decreasing size arranged in a hierarchical structure: a first buffer memory in the test controller, a second buffer memory in the bridge circuit, and a third buffer memory in the functional unit. This segmentation allows each memory unit to be optimized independently and eliminates the need for a single large interleaved DRAM, thereby reducing system complexity while maintaining high-speed testing performance.
2Productivity
If interleaved DRAM is used to provide high-speed data, then test throughput is maintained, but cost increases
Solution Approach 1:
The patent implements a nested hierarchical memory structure where the third buffer memory (smallest) is contained within the functional unit, the second buffer memory (medium) is contained within the bridge circuit, and the first buffer memory (largest) is contained within the test controller. This nesting allows data to be pre-loaded into larger upstream memories and selectively transferred to smaller downstream memories, reducing the total memory capacity required while maintaining high-speed test throughput.
3Speed
If a large buffer memory is implemented on the functional unit, then data supply speed is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements preliminary action by pre-loading test data into the first buffer memory of the test controller before testing operations begin. The test controller selectively transfers required data portions to the second buffer memory in the bridge circuit, which in turn transfers data to the third buffer memory in the functional unit as needed. This staged pre-loading and selective transfer mechanism ensures high-speed data supply to the functional unit without requiring a large buffer memory locally, thereby reducing functional unit complexity.
Data Source
AI summary
A system for testing a device under test (DUT) includes a test controller unit that includes a first memory operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern are selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit interfaces with the DUT for testing. Portions of the data pattern are selectively transferred from the second memory to the third memory for application to the DUT.