Staged Output Buffer Timing for Low-Noise Signal Conversion
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Solution Overview
Problem
Integrated circuits that convert analog signals to digital signals often experience noise due to changes in output voltage in buffer circuits, which can degrade the accuracy of the signals transmitted to microcomputers, particularly in automotive systems where precise signal conversion is critical.
Innovation Solution
The integrated circuit design incorporates a signal output circuit, a digital delay circuit, and multiple buffer circuits that operate at different timings to manage voltage changes gradually, reducing spike noise and improving signal accuracy by controlling the slew rate of the output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buffer circuit is used to transmit digital signals, then signal transmission capability is improved, but noise is generated due to voltage changes that affect the analog signal before conversion
Solution Approach 1:
The buffer circuit is divided into multiple buffer circuits (first buffer circuit and second buffer circuit) that operate at different timings. The digital signal is delayed by a digital delay circuit so that the first buffer circuit switches before the second buffer circuit, segmenting the voltage change process to reduce noise impact on the analog signal.
2Speed
If voltage changes are made rapidly in the buffer circuit, then signal transmission speed is improved, but spike noise is generated that degrades signal accuracy
Solution Approach 1:
The digital delay circuit delays the digital signal to the second buffer circuit, creating a time sequence where the first buffer circuit completes its voltage transition before the second buffer circuit begins. This preliminary action ensures that voltage changes are staged rather than simultaneous, reducing spike noise while maintaining transmission speed.
Data Source
AI summary
An integrated circuit having: a signal output circuit configured to output a first digital signal of a first logic level or of a second logic level in response to an analog signal; a first buffer circuit configured to raise and lower a voltage at a terminal of the integrated circuit in response to the first digital signal of a first logic level and a second logic level, respectively; a first digital delay circuit configured to receive a clock signal, and to delay the first digital signal, to output a resultant signal as a first delay signal, based on the received clock signal; and a second buffer circuit configured to raise the voltage at the terminal in response to the first delay signal of the first logic level, and lower the voltage at the terminal in response to the first delay signal of the second logic level.