Staged Pseudo-noise Correlator for Low Power Wireless
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Solution Overview
Problem
Conventional spread spectrum systems require large amounts of logic and increased power consumption due to the need for multiple 64-bit parallel comparators, which is counterproductive for portable wireless devices with limited power resources.
Innovation Solution
A staged pseudo-noise correlator using a multiplexer to interleave and compare portions of the incoming data stream with a known code, reducing the number of logic gates and power consumption by breaking the comparison process into stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple 64-bit parallel comparators are used to support multiple pseudo-noise codes, then the ability to detect and analyze codes is improved, but the logic area and device complexity increase significantly
Solution Approach 1:
The 64-bit parallel comparator is segmented into multiple smaller comparators that process portions of the code sequentially. Instead of comparing all 64 bits simultaneously, the system divides the comparison into stages, where each stage handles a subset of bits, thereby reducing the complexity of individual comparator circuits while maintaining the ability to support multiple codes.
Solution Approach 2:
The system dynamically reconfigures the comparison process by using a multiplexer to switch between different code portions and a shift register to present different segments of the received signal for comparison. This dynamic approach allows a single set of smaller comparators to effectively perform the work of multiple larger comparators.
2Adaptability or versatility
If multiple 64-bit parallel comparators are used to support multiple pseudo-noise codes, then the code detection capability is improved, but the power consumption increases detrimentally
Solution Approach 1:
By segmenting the comparison into stages with smaller comparators, the total power consumption is reduced because each individual comparator operates at lower power, and not all comparators need to operate simultaneously. The segmented approach allows power-efficient sequential processing.
Solution Approach 2:
The comparison process is performed periodically in stages rather than continuously in parallel. The system cycles through different code portions and segments in a periodic manner, allowing power-consuming comparison operations to be distributed over time rather than occurring simultaneously, thereby reducing peak and average power consumption.
3Adaptability or versatility
If the set of codes is expanded to support more pseudo-noise codes, then the versatility of the system is improved, but the logic area increases counter productively
Solution Approach 1:
The staged correlator with portioned comparators creates a universal structure that can handle multiple codes of varying lengths. The same hardware infrastructure (multiplexer, shift register, and smaller comparators) can be configured to support different code sets, making the system multi-functional without requiring separate dedicated hardware for each code, thereby expanding code support without proportionally increasing logic area.
Data Source
AI summary
A correlator has a feedback circuit having a first input coupled to an incoming data stream, a second input and an output. A data register is to store an incoming data stream having a number of candidate bits, the data register having an output coupled to the second input of the feedback circuit. A code register is to store a known code having a predetermined number of code bits and a comparator is to compare a portion of the incoming data stream to a portion of the known code.