Staged Firmware Load for Quick Boot Partition Access

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Solution Overview

Problem

Current boot processes in memory sub-systems are slow due to the time required to load and execute boot firmware from SPI-NOR flash drives, which also increases the bill of materials (BOM) costs and delays in achieving full operational access to non-volatile memory (NVM) devices.

Innovation Solution

The implementation of a staged firmware load process, where a small first stage firmware is quickly loaded into embedded volatile memory to provide minimal support for boot partition access via an NVM interface, allowing for rapid initialization of PCIe links and eventual loading of second stage firmware for full operational access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If boot firmware is loaded from SPI-NOR flash drives, then boot process can be completed, but boot time is slow and BOM costs increase

Engineering Contradiction:
Improveboot timeVSAvoidBOM costs
Core Design Contradiction:
Loss of timeVSEase of manufacture

Solution Approach 1:

The boot firmware is divided into two stages: a small first stage firmware that is quickly loaded into embedded volatile memory for minimal boot support, and a second stage firmware that is loaded later for full operational access. This segmentation allows the system to boot quickly using the small first stage firmware while avoiding the need for slower SPI-NOR flash drives.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary approach by using embedded volatile memory as a temporary storage for the first stage firmware, which acts as a mediator between the NVM interface and the final boot process. This intermediary enables rapid boot by avoiding direct use of slower SPI-NOR flash drives for the initial boot sequence.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If SPI-NOR flash drives are used for booting, then boot firmware can be stored, but access speed is slow

Engineering Contradiction:
Improveboot access speedVSAvoidtime to ready (TTR)
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The boot process is segmented into two stages where the first stage firmware is loaded into embedded volatile memory for rapid execution, while the second stage firmware is loaded later. This segmentation enables the system to achieve fast boot access speed during the critical initial boot phase without waiting for the slower SPI-NOR flash drive to provide full operational access.

Inventive Principle:
Principle #1Segmentation

3Productivity

If full operational access is provided immediately, then system functionality is complete, but boot time is excessive

Engineering Contradiction:
Improveboot efficiencyVSAvoidboot time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The boot process is divided into two stages: the first stage provides minimal boot support with fast access by loading a small firmware into embedded volatile memory, while the second stage provides full operational access. This segmentation enables the system to achieve high boot efficiency during the critical initial phase without requiring excessive time for full operational access.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first stage firmware provides partial boot functionality that is sufficient for initial system initialization and boot partition access, without requiring the complete second stage firmware. This partial action approach enables the system to boot efficiently by providing only the necessary minimal functionality for the boot process, avoiding the time penalty of loading the complete firmware immediately.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250199816A1Quick boot through optimized boot partition access and staged firmware load from non-volatile memory device
Publication Date: 2025.06.19 MICRON TECHNOLOGY INC
  • US20250199816A1 patent drawing
  • US20250199816A1 patent drawing
  • US20250199816A1 patent drawing

AI summary

A memory sub-system includes a non-volatile memory (NVM) memory device and a processing device operatively coupled to the memory device and to a host system. The processing device includes embedded volatile memory and retrieves, in response to power on of the memory sub-system, a read-only memory (ROM) code from an internal ROM of the processing device. The processing device executes the ROM code to load a boot code, from the memory device, into the embedded volatile memory. The processing device executes the boot code to load a first stage firmware into the embedded volatile memory. The first stage firmware is to enable access to a boot partition of the memory device before the processing device has full operational access to the memory device.