Staged Gate Voltage Control for Electrophoretic Display Artifacts

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Solution Overview

Problem

Conventional electro-optic display driving techniques induce transient voltage artifacts during power up and power down processes, leading to unwanted optical defects and variations in display characteristics due to capacitive coupling between pixel electrodes and T-wires.

Innovation Solution

Implement a two-stage or three-stage voltage control method for gate lines, where the first stage voltage is half of the gate low voltage and maintained for a specific period, followed by the full gate low voltage to minimize voltage artifacts on the electrophoretic layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional single-stage gate voltage is applied during power up and power down, then the display can be driven with simple control circuitry, but transient voltage artifacts are induced across the electrophoretic medium causing optical defects

Engineering Contradiction:
Improvevoltage control circuitryVSAvoidvoltage artifacts
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The gate voltage control is divided into multiple stages: a first stage voltage (e.g., half of gate low voltage) applied during a first time period, followed by a second stage voltage (full gate low voltage) applied during a second time period. This segmentation of the voltage application process reduces the transient voltage artifact induced across the electrophoretic medium while maintaining effective pixel transistor control.

Inventive Principle:
Principle #1Segmentation

2Object-affected harmful factors

If staged gate voltage control is implemented, then the amplitude of voltage artifacts is reduced, but the voltage control sequence becomes more complex

Engineering Contradiction:
Improvevoltage artifactsVSAvoidvoltage control sequence
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

A first stage voltage is applied to the gate line before applying the full gate low voltage. This preliminary action of applying a reduced voltage first allows the system to prepare for the full voltage transition, reducing the transient voltage artifact induced across the electrophoretic medium during the subsequent full voltage application.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces the amplitude of voltage artifacts, enhancing the stability and uniformity of the electrophoretic medium, thereby improving the optical performance and reducing display defects.

Implementation Method 1

unwanted optical defects and variations in display characteristics due to capacitive coupling between pixel electrodes and T-wires

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS12456436B2Staged gate voltage control
Publication Date: 2025.10.28 E INK CORP
  • US12456436B2 patent drawing
  • US12456436B2 patent drawing
  • US12456436B2 patent drawing

AI summary

An electro-optic display and driving method are disclosed. The electro-optic display includes a layer of electrophoretic material disposed between a common electrode and a backplane. The backplane includes an array of pixel electrodes, each coupled to a pixel transistor. A controller provides time-dependent voltages to the gate line, the source line, and the common electrode of each pixel transistor. The driving method includes applying a first stage voltage to the gate line. The first stage voltage has a first magnitude that is substantially half of a gate low voltage for placing the pixel transistor in a non-conducting state. The first stage voltage is maintained on the gate line for a first period of time. Then, a second stage voltage is applied to the gate line, where the second stage voltage has a second magnitude that is substantially the gate low voltage for placing the pixel transistor in the non-conducting state.