Staged Polynomial Multiplication for FHE Noise Management
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Solution Overview
Problem
Existing fully homomorphic encryption (FHE) schemes face significant computational overhead due to the quadratic cost of polynomial multiplication operations, particularly in cloud computing environments, and require efficient hardware acceleration for bootstrapping operations, while existing hardware solutions fail to optimize noise management across different data processing stages.
Innovation Solution
A method for designing a device that divides polynomial multiplication into interconnected data processing stages with optimized data representations, allowing each stage to have its own set of parameters, such as bit width and rounding modes, to manage noise and meet output constraints, using fixed-point arithmetic and FFT operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FFT is used for fast polynomial multiplication in FHE schemes like FHEW and TFHE, then multiplication speed is improved, but noise management becomes more difficult and bootstrapping reliability deteriorates
Solution Approach 1:
The patent divides the polynomial multiplication process into multiple data processing stages (first data processing stage, second data processing stage, etc.), where each stage performs specific operations with controlled noise accumulation. This segmentation allows the system to manage noise at each stage rather than accumulating it all at once, thereby maintaining bootstrapping reliability while using FFT for fast multiplication.
Solution Approach 2:
The patent applies different data representations and noise tolerance parameters to different data processing stages. Each stage has its own optimized parameters (such as precision levels, rounding modes) tailored to its specific role in the computation, allowing local optimization of noise management while maintaining overall system reliability.
2Device complexity
If a single data representation is used throughout the multiplication process, then device complexity is reduced, but noise management precision and computational accuracy deteriorate
Solution Approach 1:
The patent implements a dynamic data representation system where the data representation parameters (such as bit width, precision level) can change between different data processing stages. This allows the system to adapt the representation to the specific requirements of each stage, optimizing both accuracy and noise management without requiring a completely complex static system.
3Manufacturing precision
If higher precision data representations are used in all stages, then computational accuracy is improved, but computational overhead and resource consumption increase
Solution Approach 1:
The patent changes the data representation parameters dynamically across different processing stages. Stages that require higher accuracy use higher precision representations, while stages where noise management is more critical use optimized lower-precision representations. This parameter adaptation allows the system to achieve necessary computational accuracy while minimizing overall computational overhead and energy consumption.
Data Source
AI summary
A method for designing a device for performing a multiplication of polynomials in a cryptographic application. The method includes: dividing the performance of the multiplication of polynomials over at least two data processing stages of the device, wherein at least one data processing stage is arranged to receive an input operand to perform the multiplication and at least one data processing stage is arranged to provide an output signal of the multiplication, defining for each data processing stage one or more parameters related to representation of data to be processed in that data processing stage, defining one or more constraints for the output signal, determining for each data processing stage individually a value for the one or more parameters, applying the determined values for the one or more parameters in each of the data processing stages in the device for performing the multiplication of polynomials in the cryptographic application.