Staged Power-Up Circuit for Surge Current Reduction
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Solution Overview
Problem
Existing electronic devices face significant surge current issues when transitioning from standby to active mode, causing strain on power supplies and potential device failure due to large PMOS switches being turned on simultaneously, leading to increased costs and electrical migration.
Innovation Solution
A power up circuit utilizing a level detector and multiple power switches, where the charge level of the power node is monitored, and current is provided based on this level, with power switches being turned on in a controlled manner to minimize surge current and prevent simultaneous activation across multiple devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a large PMOS switch is used to provide current to the memory in active mode, then the current providing capability is improved, but surge current is generated when transitioning from standby to active state
Solution Approach 1:
The power node is pre-charged to a intermediate voltage level (e.g., 0.5V) before the main PMOS switch is activated. This preliminary charging action reduces the voltage difference when the switch turns on, thereby minimizing surge current while still enabling the switch to provide full current capability when needed.
Solution Approach 2:
The circuit dynamically controls the activation sequence of power switches based on the charging state of the power node. The first PMOS switch activates initially to charge the power node, and only after reaching the intermediate voltage level does the second PMOS switch activate to provide full power, creating a dynamic, state-dependent switching behavior.
2Object-generated harmful factors
If a delay chain is used to slow down charging the power node, then surge current is reduced, but the chip area increases due to additional inverters
Solution Approach 1:
Instead of using a delay chain of inverters, the patent introduces an intermediate voltage level as a mediator state. The power node is charged to this intermediate level first, which naturally delays the full power activation without requiring additional delay circuitry, thus reducing chip area while still controlling surge current.
Solution Approach 2:
The circuit changes the voltage parameter of the power node in stages: first charging to an intermediate voltage level (e.g., 0.5V), then transitioning to the full supply voltage level. This parameter change approach replaces the temporal delay achieved by inverters with a voltage-level-based control mechanism, eliminating the need for additional delay chain components.
3Device complexity
If multiple memories share a common input activation signal, then circuit complexity is reduced, but huge current is generated when all PMOS switches are turned on simultaneously
Solution Approach 1:
When multiple memories share a common activation signal, each memory's power node is first charged to an intermediate voltage level by its first PMOS switch before the second PMOS switch activates. This preliminary charging action ensures that even with simultaneous activation, the surge current from each memory is limited, preventing huge aggregate current while maintaining circuit simplicity.
Data Source
AI summary
Power up circuit. An example power up circuit includes a switch for charging a power node of an electronic device. A level detector is used for monitoring charge level of the power node. Further, the power up circuit includes one or more power switches for providing current to the electronic device based on the charge level.