Staged Programming for 3D NAND Memory Disturb Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-density three-dimensional memory devices face challenges in maintaining precise threshold voltage control and reducing program and erase disturb issues due to the close proximity of memory cells, which limits data storage density and increases manufacturing costs.
Innovation Solution
A two-sided staged programming operation is applied to 3D memory devices with U-shaped NAND strings, involving a preliminary, intermediate, and final programming stage, where each stage is coordinated across levels of the stack to minimize disturbance between neighboring cells, ensuring precise threshold voltage distribution and improved read margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple planes of memory cells are stacked to achieve greater storage capacity, then data storage density is improved, but program and erase disturb issues worsen due to close proximity of cells
Solution Approach 1:
The patent divides the programming operation into multiple stages (first stage, second stage, third stage) and applies them to different levels of memory cell stacks in a specific sequence. This segmentation of the programming process reduces the harmful electric field effects on neighboring cells while still achieving the desired data storage density through multi-level cell operation.
2Quantity of substance
If multiple-bit-per-cell programming is implemented, then data storage density is improved, but threshold voltage control precision worsens due to fine control requirements
Solution Approach 1:
The programming operation is divided into three distinct stages, each targeting specific threshold voltage ranges. The first stage programs to a first threshold voltage, the second stage programs to a second threshold voltage, and the third stage programs to a third threshold voltage. This staged approach enables precise control over multiple threshold voltages required for multi-bit storage without requiring extremely fine control in a single operation.
Solution Approach 2:
The first programming stage is applied as a preliminary action to establish an initial threshold voltage state before subsequent programming stages are applied. This preliminary programming creates a foundation that makes the subsequent fine-tuning in later stages more effective and easier to control.
3Quantity of substance
If memory cells are arranged in close proximity for high density, then storage capacity is improved, but electric field disturbance from neighboring cells worsens
Solution Approach 1:
The patent segments the programming operation across multiple stages and applies them to different levels in a specific sequence. By applying programming to one level only after completing programming at other levels, the patent reduces simultaneous electric field interactions between closely spaced cells, thereby reducing disturbance while maintaining high storage capacity through vertical stacking.
4Ease of manufacture
If three-dimensional memory structure is used, then manufacturing cost is reduced, but program disturb characteristics worsen
Solution Approach 1:
The staged programming approach divides the programming process into manageable stages that can be implemented in existing manufacturing processes. By applying programming to different levels in sequence rather than simultaneously, the patent reduces program disturb effects while maintaining the cost advantages of three-dimensional memory structures.
Data Source
AI summary
A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i−1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i−1).