Staged Pulse Width Modulator for Single-Step Pulse Generation
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Solution Overview
Problem
Traditional pulse width modulators face challenges in generating pulses with very small widths, as the internal delay of their multiplexers is typically larger than a single unit step, limiting the minimum pulse width to the total delay of the multiplexer, which is longer than desired.
Innovation Solution
A pulse width modulator design featuring a multiplexer with high delay stages in parallel and a low delay stage, where the final stage has a delay smaller than a single unit step, allowing for pulses with widths as small as a single unit step by balancing delays across stages and using phase signals delayed by integer multiples of unit steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a traditional multiplexer is used in the pulse width modulator, then the device structure is simple, but the minimum pulse width is limited to the total delay of the multiplexer which is larger than a single unit step
Solution Approach 1:
The multiplexer is divided into multiple stages: a first multiplexer stage with a first set of multiplexers, a second multiplexer stage with a second set of multiplexers, and a third multiplexer stage with a third set of multiplexers. Each stage processes a portion of the input signals and passes results to the next stage, allowing the final output stage to have reduced delay while maintaining overall functionality.
Solution Approach 2:
The patent introduces a time dimension by processing signals through multiple sequential stages rather than a single parallel stage. The first stage processes signals with certain delay characteristics, the second stage continues the processing, and the third stage produces the final output with minimized delay, effectively distributing the delay across time rather than concentrating it in a single spatial structure.
2Manufacturing precision
If the multiplexer delay is reduced to achieve small pulse widths, then the minimum pulse width can be a single unit step, but the device complexity increases with multiple stages and balanced delay requirements
Solution Approach 1:
Different stages of the multiplexer are designed with different delay characteristics optimized for their specific functions. The first and second stages can have larger delays suitable for their processing requirements, while the third final stage is specifically optimized to have minimal delay to enable precise pulse width control at the output.
Solution Approach 2:
The patent employs dynamic delay balancing where the delay paths are designed to ensure that signals arriving at the third multiplexer stage from the first and second stages are synchronized. This dynamic balancing allows the system to maintain precise timing control despite the complex multi-stage structure.
Data Source
AI summary
An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.