Staged Repeater Circuit for Fast Long-Interconnect Transitions
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Solution Overview
Problem
As integrated circuits (ICs) operate at higher speeds with decreasing voltages, long signal interconnects on ICs face issues with resistance and capacitance, leading to signal transition delays and potential circuit damage due to crowbar currents, which existing repeater circuits may not adequately address.
Innovation Solution
A repeater circuit design featuring a static-dynamic-dynamic configuration with specific transistor sizes and switching thresholds, including an activation stage, output stage, deactivation stage, and echo stage, to minimize RC sensitivity and power consumption by dynamically activating and deactivating output devices only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If repeater circuits are placed along signal paths to overcome resistance and capacitance effects, then signal transition speed is improved, but device complexity increases
Solution Approach 1:
The patent applies dynamic operation to the repeater circuit by using dynamic logic gates (dynamic NAND gates and dynamic inverters) that switch between high-impedance and active states. This allows the circuit to achieve fast signal transitions while reducing average power consumption and effective complexity compared to static circuits that must continuously drive all gates.
Solution Approach 2:
The repeater circuit is segmented into multiple functional blocks: dynamic logic gates, keeper circuits, and buffer stages. Each segment performs a specific function (signal inversion, signal buffering, or state maintenance), allowing the overall complex function to be divided into manageable, modular components that can be optimized independently.
2Device complexity
If simple repeater circuits like inverters or buffers are used, then device complexity is reduced, but signal transition speed deteriorates due to RC effects in long interconnects
Solution Approach 1:
The keeper circuit acts as an intermediary between the dynamic logic gate and the output buffer. It maintains the logical state during transitions and provides a stable reference, enabling the simple buffer stage to achieve fast transitions without requiring complex feedback mechanisms. The keeper circuit mediates the timing and state information to coordinate the simple components effectively.
3Power
If output devices are continuously active to drive the output node, then signal strength is maintained, but power consumption increases
Solution Approach 1:
The output buffer stage operates periodically rather than continuously. The buffer is enabled only when the keeper circuit detects a stable logical state that needs to be maintained or transmitted. During transitions, the buffer remains disabled, reducing dynamic power consumption. This periodic activation maintains sufficient output drive strength while significantly reducing average power consumption compared to continuous operation.
Data Source
AI summary
A repeater circuit. The repeater circuit includes a first output stage having two output circuits, a second output stage having two additional output circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, and responsive thereto another corresponding output circuit is configured to be activated. The output circuits drive an output signal on the output node. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the other corresponding output circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuits.