Staged Transistor Switching for Wake-Up Surge Current Control
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Solution Overview
Problem
In memory arrays, the simultaneous turning on of transistors at high operational voltage values leads to a large wake-up current, which is not effectively managed, especially at fast process corners, while at low operational voltage values, the current management is inadequate to meet short wake-up specifications.
Innovation Solution
A method where a first transistor is turned on first to provide initial current, followed by a second transistor after a predetermined time delay at high voltage, and both transistors are turned on simultaneously at low voltage, using NMOS and PMOS transistors as current paths to control the surge current effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple transistors are turned on simultaneously at high operational voltage, then the wake-up speed is fast, but the wake-up current becomes excessively large
Solution Approach 1:
The patent divides the simultaneous switching of multiple transistors into sequential stages. A first transistor is turned on initially to provide a controlled current path, followed by turning on a second transistor after a predetermined time delay. This segmentation of the switching action prevents the simultaneous current surge that would occur with simultaneous switching, thereby reducing wake-up current while maintaining acceptable wake-up speed.
Solution Approach 2:
The patent implements preliminary action by turning on the first transistor before the second transistor. The first transistor is activated initially to establish a controlled current path and prepare the circuit for subsequent switching. This preliminary action allows the circuit to wake up in a controlled manner, preventing excessive current surge when the second transistor is subsequently turned on.
2Use of energy by moving object
If a time delay is introduced between turning on transistors, then the wake-up current is reduced, but the wake-up time increases
Solution Approach 1:
The patent applies partial action by introducing a predetermined time delay only between specific transistors (first and second transistors) rather than delaying all transistor switching operations uniformly. This selective partial delay is sufficient to control the wake-up current surge while minimizing the overall impact on wake-up time. The delay is applied only where necessary to manage current flow, not across the entire switching sequence.
3Loss of time
If transistors are turned on simultaneously at low operational voltage, then the wake-up time is short, but the current management becomes inadequate
Solution Approach 1:
The patent implements dynamic switching control where the switching sequence adapts based on operational conditions. At low operational voltages, the system dynamically adjusts to turn on transistors more simultaneously to meet short wake-up specifications, while at high voltages, it employs the staged switching with time delays. This dynamic adaptation allows the system to optimize both wake-up time and current management based on the operational voltage level.
Data Source
AI summary
A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second transistor is turned on based on a second control signal delayed by a time delay from the first control signal. A second terminal of the first transistor is coupled with a second terminal of the second transistor. The second control signal is used to control a first input signal of a logic device. The logic device receives a second input signal inversed from the first control signal. An output signal of the logic device is used to control a first terminal of the second transistor.