Staged Via Formation for Semiconductor Chip Interconnects
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Solution Overview
Problem
Conventional through-silicon vias (TSVs) in semiconductor devices reduce the available space for active circuitry on the front surface, increase production costs, and face reliability challenges due to stress distribution and thermal expansion mismatch issues, while also requiring more compact and efficient interconnects for advanced portable electronics and data servers.
Innovation Solution
The development of a via structure that includes a conductive via extending through a conductive pad from the front surface to a partially tapered opening on the rear surface, with a conductive interconnect within the opening, allowing for efficient electrical connection and reduced stress through a compliant dielectric region, enabling compact and reliable interconnects between semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional through-silicon vias are used to connect bond pads to the rear surface, then electrical connection is achieved, but the available space for active circuitry on the front surface is reduced
Solution Approach 1:
The via structure is segmented into multiple components: a via hole through the bond pad, a conductive via within the hole, and a dielectric layer surrounding the conductive via. This segmentation allows for optimized space utilization and reduced stress while maintaining electrical connection functionality.
Solution Approach 2:
The dielectric layer providing stress relief is selectively positioned around the conductive via, creating local quality enhancement. This localized stress management allows the via structure to maintain electrical connection while minimizing impact on the overall chip area available for circuitry.
2Reliability
If conventional vias with thin dielectric insulation are used, then electrical connection is achieved, but stress distribution inside the vias becomes non-optimal
Solution Approach 1:
A dielectric layer is deposited around the conductive via before final assembly, providing stress relief in advance. This pre-positioned dielectric cushioning layer compensates for thermal expansion mismatches and mechanical stresses that will occur during device operation, preventing via failure.
3Reliability
If conventional vias are used in semiconductor chips bonded to polymeric substrates, then electrical connection is achieved, but the connections are under stress due to CTE mismatch
Solution Approach 1:
The dielectric layer is deposited around the conductive via before bonding the semiconductor chip to the substrate. This pre-positioned dielectric cushioning layer compensates for thermal expansion mismatches between the chip and substrate, reducing stress on the electrical connections during temperature cycling.
4Volume of moving object
If more compact physical arrangements of chips are implemented, then device size is reduced, but interconnection complexity increases
Solution Approach 1:
The via structure provides a vertical interconnection path through the bond pad and semiconductor chip, enabling three-dimensional integration. This vertical dimension allows for compact packaging arrangements while maintaining manageable interconnection complexity through standardized via structures.
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~3D
AI summary
A method of fabricating a semiconductor assembly 10 can include providing a semiconductor element 20 having a front surface 21, a rear surface 22, and a plurality of conductive pads 50, forming at least one hole 40 extending at least through a respective one of the conductive pads 50 by processing applied to the respective conductive pad 50 from above the front surface 21, forming an opening 30 extending from the rear surface 22 at least partially through a thickness of the semiconductor element 20, such that the at least one hole 30 and the opening 40 meet at a location between the front and rear surfaces, and forming at least one conductive element 60, 80 exposed at the rear surface 22 for electrical connection to an external device, the at least one conductive element extending within the at least one hole 30 and at least into the opening 40, the conductive element being electrically connected with the respective conductive pad 50.