Staged Wear-Leveling for NAND Flash Memory Controllers
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Solution Overview
Problem
As SSDs with increasing capacity require more RAM buffer to store erase count information for wear-leveling, the limited cost and chip area constraints pose a challenge in maintaining efficient wear-leveling in NAND flash memory systems.
Innovation Solution
A nonvolatile memory apparatus with a memory controller that groups chips into virtual logical groups, sets threshold values, and performs wear-leveling by using total erase count and erase count information of each logical group, allowing for staged wear-leveling and reduced chip scan time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of blocks in the memory area is increased to achieve large capacity SSD, then the storage capacity is improved, but the memory size of the RAM buffer required to store EC information of all blocks is inevitably increased, which increases cost and consumes more chip area
Solution Approach 1:
The patent divides the memory area into multiple virtual logical groups, each containing multiple physical blocks. Instead of managing all blocks uniformly, the wear-leveling process segments the search space into these virtual groups. The controller performs wear-leveling stage-by-stage: first selecting a virtual logical group based on total erase count, then searching for replaceable blocks only within that group. This segmentation allows large capacity SSDs to maintain efficient wear-leveling without requiring RAM buffer space proportional to the total number of blocks, thus reducing chip area consumption.
2Reliability
If the memory size of the RAM buffer is increased to store EC information of all blocks, then the wear-leveling performance is improved, but the cost is increased and chip area is consumed
Solution Approach 1:
The patent implements segmentation of the wear-leveling process into multiple stages. The first stage selects a target virtual logical group based on total erase count information, and the second stage searches for replaceable blocks only within that specific group. This two-stage segmented approach reduces the amount of EC information that needs to be simultaneously loaded into RAM buffer, thereby maintaining wear-leveling performance while reducing memory requirements and associated costs.
Solution Approach 2:
The patent introduces a hierarchical dimension to the wear-leveling process by organizing blocks into virtual logical groups. Instead of a single-dimensional search across all blocks, the system adds a group-level dimension to the search space. This dimensional organization allows the controller to narrow down the search scope efficiently, reducing RAM buffer requirements while maintaining wear-leveling effectiveness.
3Productivity
If the memory size of the RAM buffer is increased to store EC information of all blocks, then the wear-leveling efficiency is improved, but the available chip area is reduced
Solution Approach 1:
The patent segments the wear-leveling operation into hierarchical stages: virtual logical group selection followed by intra-group block search. This segmentation reduces the working set size required in the RAM buffer from all blocks to only those within a specific virtual logical group, thereby improving wear-leveling efficiency while minimizing chip area consumption for buffer memory.
Solution Approach 2:
The patent performs preliminary selection of a target virtual logical group based on total erase count before conducting the detailed search for replaceable blocks. This preliminary action narrows down the search scope in advance, allowing the system to maintain high wear-leveling efficiency with reduced RAM buffer requirements, thus optimizing chip area utilization.
Data Source
AI summary
Various embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the nonvolatile memory apparatus may include: a host interface; a memory controller coupled to the host interface; and a memory area including a plurality of chips controlled by the memory controller. The memory controller may be configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on the total erase count (TEC) of each logical group, and perform wear-leveling in stages.