Stagger Pulse Generation Circuit With Adjustable Delay Stages
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Solution Overview
Problem
Existing methods for generating equidistant stagger signals face challenges in controllability and circuit efficiency, with synchronous signal methods limiting delay control and asynchronous signal methods increasing circuit area and power consumption.
Innovation Solution
A stagger signal generation circuit comprising a stagger pulse generation circuit and a delay signal output circuit, which generates stagger pulse signals from inverted control signals and adjusts delay output signals through multiple signal output stages, allowing for adjustable delay without increasing circuit area or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous signal method is used to generate equidistant stagger signals, then the delay between signals is an integer multiple of clock period, but the controllability of delay is poor
Solution Approach 1:
The patent uses a ring oscillator whose oscillation frequency can be dynamically adjusted by controlling the number of conducting transistors in the signal transmission path. This allows the delay between stagger signals to be continuously adjusted rather than fixed at integer multiples of clock period, resolving the contradiction between reliability and controllability.
Solution Approach 2:
The patent changes the oscillation period parameter of the ring oscillator by adjusting the number of conducting transistors (controlled by select signals). This enables flexible control of the delay between stagger signals while maintaining stable operation, achieving both reliability and controllability.
2Ease of operation
If asynchronous signal method is used to generate equidistant stagger signals, then the controllability of delay is good, but the area of circuit layout and power consumption are significantly increased
Solution Approach 1:
The patent merges the delay control function and signal generation function into a single ring oscillator structure. By controlling the number of conducting transistors in the ring oscillator, both the delay between stagger signals and the signal generation are achieved simultaneously, avoiding the need for separate delay cells and reducing circuit area.
Solution Approach 2:
The ring oscillator serves multiple functions: it generates the oscillation signal and simultaneously provides delay control for the stagger signals. This multi-functionality reduces the overall circuit area while maintaining good controllability of the delay between signals.
3Ease of operation
If asynchronous signal method is used to generate equidistant stagger signals, then the controllability of delay is good, but the power consumption of circuit is significantly increased
Solution Approach 1:
The patent combines delay control and signal generation in a single ring oscillator, eliminating the need for separate asynchronous delay cells. This reduces the total number of active components and their associated power consumption while maintaining good delay controllability.
Solution Approach 2:
The dynamic control of conducting transistors in the ring oscillator allows for efficient power management. By adjusting the number of conducting transistors based on required delay, the circuit consumes only the necessary power for the specific application, avoiding the excessive power consumption of fully asynchronous implementations.
Data Source
AI summary
A stagger signal generation circuit is provided. The stagger signal generation circuit includes: a stagger pulse generation circuit, configured to generate a first pulse signal according to a first control signal and generate a second pulse signal according to a second control signal, the first control signal and the second control signal being inverted signals, and the first pulse signal and the second pulse signal being stagger pulse signals; and a delay signal output circuit including G signal output circuits, G being an integer greater than or equal to 2. Each non-first-stage signal output circuits receives a delay output signal outputted by a respective previous-stage signal output circuit as an input signal of a current-stage signal output circuit, and a first-stage signal output circuit receives an initial input signal as an input signal of the first-stage signal output circuit.