Staggered Backside Metal Mesh for Void-Resistant Die Packaging
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Solution Overview
Problem
The increasing density of I/O pads on semiconductor dies complicates packaging, leading to yield reduction and inefficiencies in packaging processes, particularly due to the formation of voids between dielectric layers and die-attach films.
Innovation Solution
The formation of staggered metal meshes on the backside of device dies, which are covered by dielectric layers, reduces the topology of the dielectric layer, minimizing the formation of voids and enhancing package reliability by using staggered metal meshes and dielectric layers to stabilize the die-attach film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If I/O pad density is increased to integrate more functions into smaller semiconductor dies, then functional integration is improved, but packaging difficulty increases and yield decreases
Solution Approach 1:
The patent introduces a third dimension by forming metal meshes within dielectric layers on the backside of the semiconductor die. This vertical stacking approach (multiple metal mesh layers at different depths) allows I/O pads to be redistributed in three-dimensional space rather than only on the two-dimensional die surface, enabling higher functional integration without increasing surface pad density to problematic levels.
Solution Approach 2:
The patent employs dielectric layers with embedded metal meshes as intermediary structures between the I/O pads and the packaging substrate. These intermediary layers provide mechanical support, electrical isolation, and signal routing functions, stabilizing the attachment process and reducing void formation that would otherwise occur with direct high-density pad attachments.
2Quantity of substance
If more I/O pads are packed into smaller areas, then functional integration is improved, but packaging process difficulty increases
Solution Approach 1:
The patent segments the packaging process into multiple manageable stages: forming first and second metal meshes at different locations within dielectric layers, attaching the die to a substrate, and then forming additional metal meshes. This segmentation breaks down the complex task of handling high-density I/O pads into simpler, sequential steps that are easier to control and execute.
Solution Approach 2:
The patent performs preliminary actions by pre-forming metal meshes within dielectric layers on the backside of the die before the die is attached to the packaging substrate. This preliminary structuring of the interconnect system simplifies subsequent packaging steps, as the mechanical and electrical framework is already in place to guide the attachment process.
3Adaptability or versatility
If dielectric layers are formed over metal meshes, then I/O pad redistribution is enabled, but void formation between dielectric layers and die-attach film increases
Solution Approach 1:
The patent applies local quality by positioning metal meshes at specific locations within dielectric layers rather than uniformly distributing materials throughout. The metal meshes are strategically placed to provide mechanical reinforcement exactly where needed to prevent void formation during die attachment, while maintaining the flexibility to redistribute I/O pads across different regions of the die.
4Reliability
If staggered metal meshes are formed on the backside of device dies, then dielectric layer topology is reduced and void formation is minimized, but manufacturing complexity increases
Solution Approach 1:
The patent implements a nested structure where metal meshes are embedded within dielectric layers, which are in turn attached to the semiconductor die and packaging substrate. Multiple metal mesh layers are nested at different depths within the dielectric structure, creating a hierarchical arrangement that provides mechanical stability at each level while maintaining manufacturing feasibility through standardized fabrication processes.
Data Source
AI summary
A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.