Staggered Bit Line Contacts and Vias for Memory Interconnects
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Solution Overview
Problem
Conventional memory devices face challenges in scaling interconnects due to technology-specific design rules, high resistance of polysilicon interconnects, and the need for fewer masks in fabrication, which limits storage capacity, speed, and power efficiency.
Innovation Solution
The integration of staggered bit line contacts and vias, along with source lines and source line vias, fabricated together using metal or metal alloys, reduces resistance and allows for fewer masks, enabling improved interconnects in memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon interconnects are used in conventional memory devices, then the fabrication process is well-established, but the interconnect resistance is relatively high which limits device performance
Solution Approach 1:
The patent changes the material parameter from polysilicon to metal (such as tungsten or copper), fundamentally altering the electrical resistance characteristic. This material substitution reduces interconnect resistance by several orders of magnitude while maintaining compatibility with existing semiconductor fabrication processes through established metal deposition techniques
Solution Approach 2:
The patent employs composite interconnect structures combining multiple materials - for example, tungsten plugs in contact holes combined with copper or aluminum metallization layers, or titanium nitride barrier layers with tungsten fill. These composite structures optimize both electrical performance and manufacturability by leveraging the advantages of different materials
2Manufacturing precision
If conventional interconnect fabrication is used with multiple masks, then alignment precision can be maintained, but the number of fabrication masks increases which complicates the manufacturing process
Solution Approach 1:
The patent combines multiple interconnect formation steps into a single integrated process. Specifically, bit line contacts and source line contacts are formed simultaneously using one mask pattern, and bit line vias and source line vias are formed simultaneously using another mask pattern. This merging reduces the total number of masks from four to two while maintaining alignment precision through the staggered contact design
Solution Approach 2:
The patent introduces vertical staggering of contacts at different levels to resolve horizontal alignment constraints. By offsetting bit line contacts and source line contacts in the vertical dimension (different depths), the design achieves precise electrical connections without requiring perfect horizontal alignment, thereby reducing mask complexity
3Reliability
If bit line interconnects and source line interconnects are fabricated separately, then each interconnect type can be optimized independently, but the fabrication process requires more masks and increased manufacturing complexity
Solution Approach 1:
The patent merges the fabrication of bit line interconnects and source line interconnects into unified process steps. Bit line contacts and source line contacts are formed in the same etching and filling operation, as are bit line vias and source line vias. This merging maintains independent optimization of each interconnect type while significantly reducing the number of fabrication masks and process steps
4Quantity of substance
If memory devices are scaled to increase storage capacity, then device density improves, but design rules constrain further scaling due to minimum feature sizes and spacings
Solution Approach 1:
The patent utilizes vertical dimensionality through staggered contact design to overcome horizontal scaling limits. By offsetting contacts in the vertical direction (different depths in the interconnect stack), the design achieves compact horizontal spacing that would otherwise violate minimum spacing design rules, enabling continued device scaling for increased storage capacity
Solution Approach 2:
The patent changes the interconnect material parameter from polysilicon to metal, enabling smaller feature sizes and tighter spacings. Metal interconnects have superior electrical properties that allow reduction of minimum feature dimensions and spacing requirements, thereby relaxing design rule constraints and enabling further device scaling
Data Source
AI summary
At integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.