Staggered Bond Fingers for Semiconductor Package Integration

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Solution Overview

Problem

Current semiconductor packages face challenges in efficiently arranging multiple circuit patterns within a limited area, particularly in achieving a denser integration of bond finger arrays to optimize space usage and prevent electrical short circuits during wire bonding.

Innovation Solution

The semiconductor package incorporates staggered bond finger arrays on a package substrate, with overlapping bond fingers arranged in a specific pattern to enhance integration density and prevent electrical short circuits, allowing for efficient wire bonding and improved design flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bond finger arrays are arranged in a conventional non-overlapping pattern, then electrical short circuits are prevented, but integration density and space usage are reduced

Engineering Contradiction:
Improveprevention of electrical short circuitsVSAvoidintegration density of bond fingers
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent transitions from a one-dimensional linear arrangement of bond fingers to a two-dimensional staggered grid pattern. Bond fingers are arranged in multiple rows and columns with offset positioning, allowing vertical and horizontal overlap patterns that increase the number of bond fingers per unit area while maintaining electrical isolation through precise spatial separation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The staggered arrangement creates a nested pattern where bond fingers from different arrays interleave with each other in a coordinated manner. The first and second bond finger arrays are positioned such that their fingers alternate in the vertical direction, creating a compact nested structure that maximizes space utilization without causing electrical interference.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If bond finger arrays are arranged to maximize integration density, then space usage is optimized, but risk of electrical short circuits during wire bonding increases

Engineering Contradiction:
Improveintegration density of bond fingersVSAvoidprevention of electrical short circuits
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent employs asymmetric positioning of bond fingers within the staggered grid, where the horizontal and vertical spacing patterns are deliberately non-uniform. This asymmetric arrangement creates irregular spacing that prevents regular wire bonding paths from accidentally bridging adjacent bond fingers, thereby reducing short circuit risk while maintaining high density.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

Different regions of the bond finger array have locally optimized spacing characteristics. Areas with higher wire bonding activity have greater vertical separation, while regions with lower activity can have tighter spacing. The staggered pattern allows local adjustment of finger positions to match the specific wire bonding requirements of different chip pad locations.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If conventional bond finger arrangements are used, then manufacturing processes are simple, but design flexibility and integration options are limited

Engineering Contradiction:
Improvesimplicity of manufacturing processVSAvoiddesign freedom for package configurations
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The bond finger array is segmented into multiple independent first and second arrays that can be independently configured and optimized. Each array can be designed with specific spacing and positioning characteristics suited to different chip types and wire bonding patterns, allowing flexible adaptation to various package designs while maintaining a systematic manufacturing approach.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11444052B2Semiconductor package including a package substrate including staggered bond fingers
Publication Date: 2022.09.13 SK HYNIX INC
  • US11444052B2 patent drawing
  • US11444052B2 patent drawing
  • US11444052B2 patent drawing

AI summary

A semiconductor package includes a package substrate including: first and second bond finger arrays, each of the first and second finger arrays arranged in a first direction on a surface of the package substrate; a first semiconductor chip disposed on the surface of the package substrate and including a first chip pad array corresponding to the first bond finger array; a second semiconductor chip disposed on the surface of the package substrate and including a second chip pad array corresponding to the second bond finger array; first bonding wires connecting bond fingers of the first bond finger array to chip pads of the first chip pad array; and second bonding wires connecting bond fingers of the second bond finger array to chip pads of the second chip pad array.