Staggered-Layer Capacitor Array for Millimeter Wave Low Impedance
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Solution Overview
Problem
Designing a capacitor array with a staggered layer structure for the millimeter wave frequency band that effectively addresses conduction noise suppression and conduction loss while adhering to the CMOS process design rules is a challenge in high-frequency circuits.
Innovation Solution
A capacitor unit with a staggered-layer structure is developed, comprising odd and even layers with specific slots, vias, and connecting portions, allowing for flexible connections and arrangements that form a capacitor array suitable for CMOS processes, providing wide bandwidth, low impedance, and low conduction loss for millimeter wave frequency applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional multi-layer capacitors are used with laminated dielectric layers and alternating inner electrodes, then the capacitor structure is simple and easy to manufacture, but the conduction loss is high and bandwidth is limited for millimeter wave frequency band
Solution Approach 1:
The patent transitions from a conventional planar multi-layer capacitor structure to a three-dimensional staggered-layer structure. The odd and even layers are offset from each other in the vertical dimension, creating a staggered arrangement that increases the effective capacitance area without increasing the planar footprint. This dimensional change enables lower equivalent series inductance (ESL) and reduced conduction loss while maintaining compatibility with CMOS fabrication processes.
2Adaptability or versatility
If conventional capacitor designs are used, then the design follows standard CMOS processes, but the bandwidth is limited and impedance is not sufficiently low for millimeter wave applications
Solution Approach 1:
The capacitor structure is segmented into two independent sets of layers: odd layers (101, 103, 105, 107) and even layers (102, 104, 106, 108). Each set can be independently connected to different potential nodes (e.g., power and ground). This segmentation allows for flexible configuration to achieve desired electrical characteristics while maintaining manufacturing feasibility through standard via and slot formation processes.
Solution Approach 2:
The patent employs asymmetric positioning of odd and even layers relative to each other, creating a staggered configuration rather than a symmetric stacked arrangement. The odd layers are horizontally offset from the even layers, which creates asymmetric current paths that reduce inductance and improve bandwidth performance while remaining compatible with CMOS design rules.
3Reliability
If the capacitor array is designed with staggered layer structure for millimeter wave frequency band, then the bandwidth increases and impedance decreases, but the design complexity and manufacturing difficulty increase
Solution Approach 1:
The staggered-layer capacitor structure serves multiple functions simultaneously: it provides capacitance for high-frequency bypassing, acts as an electromagnetic shield, and can be integrated into power delivery networks. The same basic unit can be replicated and arranged in various patterns (2x2, 3x3, etc.) to scale the capacitance value while maintaining the beneficial electrical characteristics, making it universally applicable across different millimeter wave circuit designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitor array with a staggered-layer structure achieves stable bypass capacitor design with wide bandwidth and low impedance, reducing conduction loss and resonation, making it suitable for power source traces in millimeter wave frequency bands.
Implementation Method 1
a capacitor unit with staggered-layer structure for a capacitor array, comprising a plurality of odd layers, wherein each of the plurality of odd layers is formed with a first slot... a plurality of first connecting portion corresponding to the plurality of odd layers, formed in the first slot, and configured to connect the first via and the plurality of odd layers
Data Source
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AI summary
A capacitor array (10, 100, 110) with staggered-layer structure includes a plurality of capacitor units. Each of the plurality of capacitor units comprises a plurality of odd layers (101) formed with a first slot (105); a first via (V1) formed in the first slot (105); a plurality of first connecting portion (103) configured to connect the first via (V1) and the plurality of odd layers (101); a plurality of even layers (102) formed with a second slot (105); a second via (V2) formed in the second slot (105); a plurality of second connecting portion (104) configured to connect the second via (V2) and the plurality of even layers (102); wherein one of the plurality of odd layers (101) is adjacent to one of the plurality of even layers (102) to form a staggered-layer structure. The capacitor unit with staggered-layer structure provides is applicable for CMOS process to be utilized as a power source trace as well as density cell to satisfy design rule for metal density. A plurality of the capacitor units may be coupled and arranged to be the capacitor array adapted to at least one of alignment, non-alignment, overlapping and non-overlapping designs. Moreover, the capacitor array with staggered-layer structure provides characteristics of wide bandwidth, smooth and low impedance, and low conduction loss for bypass capacitor design, which is suitable for power source trance for millimeter wave frequency band.