Staggered Capture Clocks for Low Power Scan Testing
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Solution Overview
Problem
Scan-based tests for integrated circuits face challenges in reducing peak power during capture cycles at high clock speeds, leading to potential false failures and yield loss due to excessive heat dissipation and power-related issues, with existing solutions either being costly or requiring significant implementation and verification efforts.
Innovation Solution
The method involves staggering capture clocks to CPU cores and cache using dynamic Fast Test Mode (FTM) engines, counting pulses during a first time window, and generating pulses during a second time window based on the counted pulses, allowing for at-speed testing while minimizing peak power and maintaining defect coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan operations are run at higher clock speeds to reduce test time, then productivity is improved, but power consumption increases causing flip-flops and gates to behave incorrectly
Solution Approach 1:
The patent divides the clock distribution into separate domains: a functional clock domain for normal operation and a test clock domain for scan operations. This segmentation allows independent control of clock frequencies - high speed for testing when power is managed, and normal speed for functional operation, resolving the contradiction between test speed and power consumption.
Solution Approach 2:
The patent implements dynamic clock gating control where clock signals to functional blocks are selectively enabled or disabled based on operational mode. During scan operations, functional blocks receive gated clocks to minimize power consumption while scan chains operate at high speeds, allowing the system to adapt power delivery dynamically to operational requirements.
2Productivity
If scan operations are run at higher clock speeds to reduce test time, then productivity is improved, but reliability deteriorates due to electrical and thermal stressing
Solution Approach 1:
The patent segments the circuit into scan chains and functional blocks with separate clock domains. This allows high-speed clocking to be applied only to scan chains during testing while functional blocks operate normally or in low-power mode, preventing electrical and thermal stress on the entire circuit and maintaining reliability.
Solution Approach 2:
The patent implements periodic clock gating where functional blocks receive clock signals only during functional operation periods and are clock-gated during scan test periods. This periodic activation pattern reduces cumulative electrical and thermal stress on functional blocks, preventing reliability degradation while maintaining high test speeds.
3Reliability
If dynamic power consumption during scan test is reduced, then reliability is improved, but test time increases
Solution Approach 1:
The patent segments power management by creating separate clock domains for scan and functional operations. This allows full-speed scan operations to proceed without power gating delays, while functional blocks use selective clock gating to reduce power consumption, achieving both fast testing and reliability.
Solution Approach 2:
The patent introduces clock gating cells as intermediary components between the clock source and functional blocks. These cells act as mediators that can rapidly enable or disable clock signals to functional blocks during scan operations, reducing dynamic power consumption without impacting scan chain speed and thus not increasing test time.
Data Source
AI summary
A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.