Staggered Dual-Side Chip Interconnect for Shorter PCB I/O Routing
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Solution Overview
Problem
The increasing circuit density and clock speeds in printed circuit boards (PCBs) lead to higher insertion loss and crosstalk noise, particularly in inter-chip communication, limiting performance due to constrained routing path lengths and competing demands for high-speed I/O pins and transient power supply components.
Innovation Solution
A stacked and staggered chip package layout on opposite sides of a PCB, with low-latency pins aligned along a single side and decoupling capacitors positioned across from the chip packages, allowing direct routing connections and efficient thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If chip packages are mounted on opposite sides of a PCB directly across from each other, then inter-chip path length is minimized, but layout of other components becomes constrained
Solution Approach 1:
The patent applies asymmetry by staggering the chip packages laterally rather than positioning them directly across from each other. This asymmetric offset arrangement allows signal pins to be routed across the PCB thickness while providing space for other components to be placed on either side of the chip packages, thus resolving the contradiction between minimizing inter-chip path length and maintaining component placement flexibility
Solution Approach 2:
The patent utilizes the third dimension (PCB thickness) for signal routing between chip packages mounted on opposite sides. By routing signals through vias across the PCB thickness rather than along the surface, the patent minimizes inter-chip path length while the lateral staggering provides two-dimensional space for other components, effectively using dimensional space to resolve the contradiction
2Adaptability or versatility
If chip packages are mounted side-by-side on the same side of a PCB, then component placement is flexible, but inter-chip path length increases
Solution Approach 1:
The patent moves chip packages from a two-dimensional side-by-side arrangement to a three-dimensional stacked arrangement on opposite PCB sides. This dimensional transition reduces the signal path from several centimeters to approximately the PCB thickness, while the lateral staggering maintains placement flexibility for other components
3Adaptability or versatility
If high-speed I/O pins are routed across long path lengths, then routing flexibility is maintained, but insertion loss and crosstalk noise increase
Solution Approach 1:
The patent routes high-speed I/O signals through the PCB thickness dimension using vias, reducing the signal path from surface-level routing to through-hole routing. This dimensional change minimizes the path length to approximately the PCB thickness, significantly reducing insertion loss and crosstalk noise while maintaining routing flexibility through via placement options
Solution Approach 2:
The patent pre-positions signal pins on the chip packages to align with corresponding pins on opposing chips, and pre-routes the interconnect paths through the PCB structure. This preliminary arrangement of pins and paths minimizes the actual signal travel distance, reducing harmful effects before signals are transmitted
Data Source
AI summary
Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.