Staggered Chip Stacking Layout for Bonding Wire Reliability
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Solution Overview
Problem
In stack-type semiconductor packages, the structural reliability of bonding wires is compromised when upper semiconductor chips are stacked over lower ones, as the upper chips can screen and physically damage the bonding wires, leading to reliability issues during the stacking process.
Innovation Solution
The semiconductor package design includes semiconductor chips with specific pad arrangements, where each chip has first and second pads disposed along intersecting edge lines, allowing for staggered and offset stacking to expose pads and reduce wire bonding angles, thereby minimizing physical damage to bonding wires and improving structural reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If upper semiconductor chips are stacked over lower semiconductor chips, then vertical integration and space utilization are improved, but the structural reliability of bonding wires deteriorates due to screening and physical damage
Solution Approach 1:
The patent transitions from a conventional aligned vertical stacking arrangement to a staggered three-dimensional arrangement where chips are offset both vertically and horizontally. This dimensional change allows bonding wires to extend laterally without being screened by upper chips, maintaining wire integrity while achieving high vertical integration. The staggered configuration creates lateral clearance that prevents physical damage to bonding wires during stacking.
Solution Approach 2:
The patent introduces asymmetric offset distances between stacked chips in different directions (first offset distance in first direction, second offset distance in second direction). This asymmetric arrangement optimizes the exposure of chip pads while maintaining adequate clearance for bonding wires, resolving the contradiction between vertical integration and bonding wire reliability through non-uniform spatial distribution.
2Ease of manufacture
If chips are stacked in aligned manner, then manufacturing simplicity is maintained, but pad exposure and wire bonding reliability deteriorate
Solution Approach 1:
The patent performs preliminary positioning of chips in a staggered arrangement before wire bonding, with predetermined offset distances that ensure pad exposure and bonding wire clearance are already optimized. This preliminary action eliminates the need for complex real-time adjustments during bonding, maintaining manufacturing simplicity while ensuring bonding reliability through pre-configured spatial relationships.
3Reliability
If offset stacking is implemented, then bonding wire reliability is improved, but device complexity increases
Solution Approach 1:
The patent manages device complexity by controlling and standardizing the offset parameters (first offset distance and second offset distance) within specific ranges. By defining bounded parameter spaces rather than arbitrary complex arrangements, the patent achieves bonding wire reliability through parameter optimization while maintaining manufacturability and avoiding excessive complexity.
Data Source
AI summary
A semiconductor package includes a package substrate, a first semiconductor chip disposed over the package substrate, and a second semiconductor chip stacked over the first semiconductor chip. Each of the first and second semiconductor chips includes a chip body, first chip pads disposed in a first region of a surface of the chip body, and second chip pads disposed in a second region of the surface of the chip body. The first chip pads of the first semiconductor chip and the first chip pads of the second semiconductor chip are disposed at opposite sides from each other over the package substrate. The second chip pads of the first semiconductor chip and the second chip pads of the second semiconductor chip are disposed at opposite sides from each other over the package substrate.