Staggered Circuit Module Arrangement for Signal Integrity
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Solution Overview
Problem
High-density circuit module stacking at the package level leads to increased impedance and signal quality deterioration due to longer wiring lengths and varying capacitances and inductances in the fly-by method, which hinders high-speed operation.
Innovation Solution
The implementation of a staggered arrangement of solid-state circuit components on a circuit board, where each device is partially overlapped in the height direction to reduce wiring length and impedance variation, eliminating the need for stacking and allowing for a shorter distance to the input/output circuit, thereby reducing capacitance and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked at package level to achieve high-density mounting, then mounting density is improved, but wiring length increases and impedance varies causing signal quality deterioration
Solution Approach 1:
The patent transitions from vertical stacking (3D packaging) to a planar staggered arrangement where chips are positioned at different horizontal offsets. This dimensional change allows chips to be densely packed without requiring long vertical interconnections, thereby maintaining high mounting density while reducing wiring length and impedance variation for high-speed signal integrity.
2Adaptability or versatility
If wiring is extended to connect stacked chips, then connectivity between chips is achieved, but impedance increases and signal quality deteriorates
Solution Approach 1:
The patent segments the interconnection architecture by eliminating the need for long vertical wires through stacking. Instead, each chip connects to the substrate through short individual pathways, and chips communicate through the substrate plane. This segmentation of the connection path reduces the length of critical signal traces, minimizing impedance effects and maintaining signal quality while achieving full chip connectivity.
3Area of stationary object
If chips are arranged in a compact stacked configuration, then space utilization is improved, but wiring length increases causing higher impedance
Solution Approach 1:
The patent resolves the conflict between compact arrangement and wiring length by changing the interconnection dimension. Rather than connecting chips vertically through long wires, the staggered planar arrangement allows chips to be closely spaced while maintaining short horizontal connection paths through the substrate, effectively decoupling space utilization from wiring length.
Data Source
AI summary
In an electrical component including a solid-state circuit portion and a substrate connecting portion, the solid-state circuit portion includes: a supporting surface faced to and supported by the substrate connecting portion; and an opposing surface which is widened outside the supporting surface and which has an area enough to be opposed to another solid-state circuit portion. This structure makes it possible to arrange, on a circuit board, a plurality of the electrical components in a staggered manner in a height direction.