Staggered Clock Latch Circuit for Transient Disturbance Protection
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Solution Overview
Problem
Existing electronic circuitry is insufficient in protecting against transient disturbances, particularly in nanotechnologies where logic transition times are short, leading to propagation of disturbing pulses and inadequate detection of errors affecting both latches and combinatory logic circuits.
Innovation Solution
The implementation of staggered clock signals for odd and even stages, with monitoring mechanisms that compare output and input values at specific observation times to detect transient disturbances and improve error detection and correction, while also enhancing simulation techniques to assess disturbances throughout the clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logic transition times are reduced to increase productivity, then processing speed is improved, but the circuit becomes more susceptible to transient disturbances
Solution Approach 1:
The circuit is divided into successive stages with alternating odd and even stages, each having its own latch. This segmentation allows independent monitoring and protection of each stage, enabling the circuit to maintain high speed operation while providing targeted protection against transient disturbances in each segment.
Solution Approach 2:
Monitoring circuits are implemented that compare output and input values of latches and combinatory logic circuits. When a transient disturbance is detected, the monitoring circuit generates an error signal that triggers correction mechanisms, providing feedback-based protection that maintains reliability without sacrificing processing speed.
2Reliability
If monitoring circuits are added to detect transient disturbances, then reliability is improved, but device complexity increases
Solution Approach 1:
The monitoring function is merged with the existing latch structure by using the same latch to store both the input value and output value for comparison. The monitoring circuit reuses existing signals and structures, avoiding the need for completely separate monitoring hardware and reducing overall device complexity.
Solution Approach 2:
The monitoring circuit creates a copy of the input value stored in the latch and compares it with the output value. This copying approach allows for simple comparison logic using basic logic gates rather than complex monitoring mechanisms, reducing the complexity of the monitoring circuit while maintaining effective transient disturbance detection.
3Measurement precision
If duplicate latches are used for error detection, then measurement precision is improved, but device complexity increases
Solution Approach 1:
Instead of using full duplicate latches for every stage, the invention applies monitoring selectively to detect transients that could propagate to subsequent stages. The monitoring is performed at critical points where transient propagation would have the most impact, providing sufficient error detection capability without the overhead of complete duplication throughout the entire circuit.
Data Source
AI summary
The circuitry comprises successive stages, each comprising a combinatory logic circuit connected to the input of a first latch. Staggered clock signals are respectively associated with the first latches of the odd and even stages. Means for detecting a transient disturbance affecting the first latch of a stage and liable to propagate downstream, compare, in each stage, a value present on the output of the first latch of the stage considered at an observation time with a value present on the input of said first latch at a predetermined observation time taking account of the various propagation times.