Staggered Clock Distribution for Scan Flip-Flop Power Reduction
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Solution Overview
Problem
In scan designs, excessive switching activity due to simultaneous loading of data in flip-flops leads to high power usage, voltage droop, and inefficient power distribution, with limited control over don't care bits contributing to unnecessary power consumption.
Innovation Solution
A clock distribution network with partitioned clock signal networks and controlling logic, including shift registers and AND gates, is used to stagger the clock signal, ensuring only one group of flip-flops receives the signal at a time, thereby reducing power usage by limiting simultaneous activity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is loaded into all flip-flops simultaneously using compression procedures, then test data loading speed is improved, but power consumption increases excessively due to high switching activity
Solution Approach 1:
The patent divides the clock signal distribution into multiple partitioned networks, each serving a specific group of flip-flops. The controlling logic segments the clock signal timing so that different groups receive clock signals at different times, thereby segmenting the switching activity across time rather than having all flip-flops switch simultaneously. This maintains the ability to load test data efficiently while distributing power consumption over multiple time slots.
Solution Approach 2:
The patent implements periodic action by using a shift register to generate staggered clock signals that are distributed periodically to different groups of flip-flops. Instead of a single simultaneous clock edge, the system uses multiple periodic clock cycles with controlled timing, where each cycle activates a specific subset of flip-flops. This periodic staggering reduces peak power consumption while maintaining overall test data loading productivity.
2Reliability
If continuous bursts of data are loaded into flip-flops, then test coverage is improved, but voltage droop occurs due to excessive current draw from the power grid
Solution Approach 1:
The patent segments the flip-flop population into multiple groups, each served by a partitioned clock signal network. The controlling logic ensures that only one group receives the clock signal at any given time, segmenting the current draw from the power grid. This prevents the excessive simultaneous current draw that causes voltage droop, while still achieving comprehensive test coverage by systematically activating all groups over time.
Solution Approach 2:
The patent introduces controlling logic as an intermediary between the main clock signal network and the partitioned clock signal networks. This intermediary manages the distribution timing, ensuring that clock signals are staggered across different groups. The intermediary prevents direct simultaneous activation of all flip-flops, thereby mediating the power grid load and preventing voltage droop while maintaining test coverage.
3Quantity of substance
If don't care bits are used in compression procedures, then data compression ratio is improved, but switching activity increases due to random 0's and 1's in don't care bits
Solution Approach 1:
The patent applies local quality by treating different groups of flip-flops differently through partitioned clock networks. While don't care bits may contain random transitions, the staggered clock distribution ensures that switching activity in one group does not simultaneously add to the total power consumption. Each group experiences controlled local switching activity, and the cumulative effect is reduced overall power loss compared to simultaneous activation of all groups.
Data Source
AI summary
Exemplary embodiments of the present disclosure relate to a clock distribution network for a scan design, which may include, for example, a clock signal network(s), and a plurality of partitioned clock signal networks coupled to the clock signal network(s) through a controlling logic(s); where the controlling logic(s) may be configured to stagger a clock signal from the clock signal network(s), and where each of the partitioned clock signal networks may be connected to a group of flip-flops. A first partitioned clock signal network of the partitioned clock signal networks may be connected to a first group of flip-flops and a second partitioned clock signal network of the partitioned clock signal networks may be connected to a second group of flip-flops, and where the first group of flip-flops may be different than the second group of flip-flops. The controlling logic(s) may include a shift register(s).