Staggered Clocks for IC Testing Voltage Stability
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Solution Overview
Problem
In multi-processor environments, testing a processor for structural defects can cause voltage drops due to current fluctuations, affecting other processors sharing the same voltage rail, leading to timing failures, and existing methods struggle to adjust the toggle rate within a single partition of a processing core effectively during testing.
Innovation Solution
Staggering clocks within a computing element, such as a processing core, by creating clipped clocks with different waveforms for various portions, reduces voltage drops during testing by varying the toggle rate within the partition, thereby minimizing the impact on other processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a processor is tested at high toggle rate to improve test quality, then test reliability is improved, but voltage drops occur affecting other processors on the same voltage rail
Solution Approach 1:
The processing core is divided into multiple partitions, and clocks are staggered across these partitions so that not all flip-flops toggle simultaneously. This segmentation of the clocking operation reduces peak current demand while maintaining comprehensive test coverage across all processor elements.
Solution Approach 2:
Clocks are applied periodically but with staggered timing across different partitions. The periodic clocking continues at the required frequency for test quality, but the staggered phase distribution spreads the current demand over time, preventing voltage drops.
2Object-affected harmful factors
If clocks are staggered within a partition to reduce voltage drops, then voltage stability is improved, but test coverage may be reduced
Solution Approach 1:
The core is segmented into partitions with staggered clocks, but the segmentation is designed so that all partitions are eventually tested. The staggered timing prevents simultaneous toggling while ensuring complete test coverage through systematic progression across all partition elements.
Solution Approach 2:
The clock staggering is dynamically configured to ensure that over the test period, all partitions receive adequate testing. The staggered pattern is optimized to maintain both voltage stability and comprehensive test coverage by adjusting which partitions are active at different time intervals.
3Productivity
If multiple processors are tested simultaneously to improve productivity, then test throughput is improved, but voltage drops increase affecting timing failures
Solution Approach 1:
Each processor under test is divided into partitions with internally staggered clocks. This segmentation allows multiple processors to be tested simultaneously while each processor's internal staggering prevents excessive current draw, maintaining voltage stability and preventing timing failures across the multi-processor system.
Solution Approach 2:
Multiple processors are tested in parallel (merged testing), but each processor employs internal clock staggering. The combination of parallel processor testing with individual processor clock management achieves high throughput while preventing voltage-related timing failures through the staggered clocking mechanism.
Data Source
AI summary
During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.