Staggered Column Superjunction for Power MOSFET Trade-Offs

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional power MOSFETs face a trade-off between low on-resistance (Rds-on) and high breakdown voltage (BV), with superjunction devices experiencing unstable Unclamped Inductive Switching (UIS) due to process variations and varying Rds-on and BV across a wafer, particularly in termination and corner regions.

Innovation Solution

A staggered column vertical superjunction semiconductor device is developed, featuring alternating P-type and N-type columns with different depths in active and termination regions, allowing for adjusted breakdown voltage and on-resistance characteristics, with deeper columns in termination regions for higher BV and shallower columns in active regions for lower Rds-on.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If conventional lowly doped drift region is used to provide high breakdown voltage, then breakdown voltage is improved, but on-resistance increases dramatically

Engineering Contradiction:
Improvebreakdown voltageVSAvoidon-resistance
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The drift region is segmented into alternating P-type and N-type doped columns (superjunctions) instead of a uniform lowly doped region. This segmentation allows the device to achieve high breakdown voltage through complete depletion of columns while maintaining lower on-resistance through the presence of highly doped column regions that provide conduction paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the drift region are given different doping characteristics - P-type columns and N-type columns with specific doping concentrations and depths are created to optimize local electrical properties. The staggered column configuration creates local variations in depletion characteristics that improve overall device performance.

Inventive Principle:
Principle #3Local quality

2Reliability

If superjunction devices are used to achieve low on-resistance and high breakdown voltage, then the trade-off between Rds-on and BV is improved, but UIS performance becomes unstable due to process variation

Engineering Contradiction:
ImproveRds-on and BV characteristicsVSAvoidUIS performance stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The invention changes the depth parameter of P-type columns in termination regions relative to active regions. By making P-type columns in termination regions deeper than those in active regions, the device compensates for process variations and ensures that termination regions do not break down before active cell regions during UIS conditions, thereby stabilizing UIS performance.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention introduces a vertical depth dimension differentiation between termination and active regions. By varying the P-type column depth in the vertical dimension across different device regions, the patent achieves region-specific breakdown voltage characteristics that stabilize overall UIS performance despite process variations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If uniform P-type column depth is used across all regions, then manufacturing is simplified, but termination regions may break down before active cell regions during UIS

Engineering Contradiction:
Improvecolumn formation processVSAvoidUIS robustness
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The invention applies different P-type column depths to different device regions - termination regions receive deeper P-type columns while active regions receive shallower columns. This local differentiation ensures that termination regions have higher breakdown voltage to prevent premature breakdown during UIS, while maintaining relatively simple manufacturing through region-specific processing steps.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach stabilizes UIS performance by maintaining high breakdown voltage in termination regions while reducing on-resistance in active regions, effectively addressing the trade-off between BV and Rds-on, and minimizing damage from avalanche conditions.

Implementation Method 1

Dopants having a second conductivity type may be implanted through the openings to form first implanted regions

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Implementation Method 2

A second semiconductor layer may be grown on top of the first semiconductor layer

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 3

the dopants of second conductivity type may be diffused to form the columns of second conductivity type

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS8900949B2Staggered column superjunction
Publication Date: 2014.12.02 ALPHA & OMEGA SEMICONDUCTOR INC
  • US8900949B2 patent drawing
  • US8900949B2 patent drawing
  • US8900949B2 patent drawing

AI summary

A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.