Staggered Core Activation for Power Surge Management
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Solution Overview
Problem
Multicore systems face challenges in managing sudden power surges when multiple cores transition from an idle to an operational state due to simultaneous activation of components, which can lead to voltage drops and performance issues, as conventional bulk capacitors may not adequately address these surges.
Innovation Solution
A staggering mechanism is implemented where cores are grouped and transitioned to an operational mode in a staggered fashion based on a stagger value or group number, using a configuration register and timer signals to synchronize core activation, thereby limiting the sudden surge of power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cores transition from idle mode to operational mode simultaneously, then system responsiveness and processing capability are improved, but sudden power surge occurs causing voltage drops and performance degradation
Solution Approach 1:
The patent segments the core transition process by dividing cores into multiple groups (first group, second group, etc.) and assigning different stagger values to each group. This segmentation allows cores to transition from idle mode to operational mode in a distributed manner rather than simultaneously, thereby reducing the sudden power surge while maintaining overall system responsiveness.
Solution Approach 2:
The patent implements periodic action through the use of stagger values and group-based transition timing. Cores in different groups transition at different periodic intervals determined by their assigned stagger values. This periodic staggering ensures that power consumption increases gradually over time rather than in a single sudden surge, preventing voltage drops while still achieving timely system response.
2Reliability
If bulk capacitor is used to address power surge, then voltage stability is improved, but device complexity and implementation constraints increase
Solution Approach 1:
The patent changes the parameter of transition timing by introducing stagger values assigned to different core groups. Instead of all cores transitioning at the same time (original parameter), cores now transition at different time offsets determined by their group's stagger value. This parameter change effectively reduces power surge without requiring additional hardware components like large bulk capacitors, thereby maintaining voltage stability while avoiding increased device complexity.
3Power
If cores are grouped with different stagger values, then power surge is reduced, but transition time and system activation delay increase
Solution Approach 1:
The patent applies partial action by having only certain groups of cores transition at any given time rather than all cores simultaneously. The stagger value assignment ensures that while some cores are transitioning, others remain in idle mode or are transitioning at different rates. This partial transition approach reduces the peak power surge while the cumulative effect of all groups transitioning eventually achieves full system operational status, balancing power management with acceptable transition time.
Data Source
AI summary
A system includes a first and a second group of cores in a multicore system. Each core of the first/second group is configured to process data. Each core within the first/second group is configured to enter into an idle state in response to being idle for a first/second period of time respectively. Every idle core in the first/second group is configured to transition out of the idle state and into an operational mode in response to receiving a signal having a first/second value respectively and further in response to having a pending operation to process.