Staggered DLL Clocking for N-Detect QED Command Path
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Solution Overview
Problem
As DRAM's target CLK frequency increases, CAS latency control becomes more challenging due to clock domain crossing issues, particularly at fast tCK operations, requiring accurate CL calculation to ensure timely data delivery while minimizing unnecessary clocking and power consumption.
Innovation Solution
The implementation of staggered clocking within the command path of a memory device using a shifter circuit with flip-flops controlled by CAS latency signals, allowing the read command to be delayed and realigned with the DLL clock, and the use of N-Detect QED arrangements to determine and account for intrinsic delays, thereby reducing command decode and delay path delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased to improve performance, then productivity increases, but CAS latency control becomes more difficult and timing accuracy deteriorates
Solution Approach 1:
The command path is divided into multiple pipeline stages with staggered clocking. Each stage is clocked at different phases, allowing the system to handle high-frequency operations while maintaining precise timing control through phased clock signals rather than a single monolithic clock domain.
Solution Approach 2:
The system uses dynamic phase adjustment of clock signals to the shifter circuit based on detected timing characteristics. The staggered clocking phases are dynamically selected and adjusted to optimize CAS latency control for different operating conditions and timing corners.
2Adaptability or versatility
If clock domain crossing is implemented to enable data transfer between domains, then adaptability improves, but timing accuracy and domain crossing reliability deteriorate
Solution Approach 1:
A shifter circuit with staggered clocking acts as an intermediary between the command clock domain and the DLL clock domain. This intermediate circuit uses multiple phased clock signals to gradually transition commands between domains, maintaining timing accuracy while enabling domain crossing.
Solution Approach 2:
The system adds a temporal dimension to domain crossing by using staggered clock phases. Instead of direct domain crossing, commands are transferred through multiple phased stages, effectively adding time as an additional dimension to the crossing process and improving reliability.
3Measurement precision
If command decode and delay path is extended to achieve precise latency control, then measurement precision improves, but device complexity and power consumption increase
Solution Approach 1:
The shifter circuit uses periodic staggered clock phases to achieve precise latency control. By cycling through multiple phased clock signals in sequence, the system achieves fine-grained delay control without requiring excessively long combinational logic paths, thereby reducing complexity.
4Productivity
If continuous clocking is used to maintain readiness, then productivity is maintained, but power consumption increases
Solution Approach 1:
The staggered clocking system enables periodic or burst-mode operation where clock phases are activated only when needed for command processing. This allows the system to maintain operational readiness while reducing power consumption during idle periods by selectively enabling only the necessary clock phases.
Data Source
AI summary
Apparatuses and methods are described for meeting timing and latency requirements using staggered clocking within the command path. In one example, an apparatus is disclosed that includes a timing circuit configured to provide an internal clock signal; a clock stagger circuit configured to receive the internal clock signal from the timing circuit and to generate at least one delayed internal clock signal; and a shift circuit arranged in a command decode and delay path of a command signal, coupled to the timing circuit and to the clock stagger circuit, and configured to capture the command from an external clock domain into an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal