Staggered Drive Circuit Timing for CMOS Current Spike Reduction
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Solution Overview
Problem
In touch screen and display circuits, the simultaneous logic state transitions in multiple CMOS inverter pairs lead to increased short circuit current spikes, which can result in supply voltage drops, necessitating either a decoupling capacitor or a larger regulator, both of which may not be feasible due to space constraints.
Innovation Solution
The implementation of a drive circuit that delivers staggered copies of input signals to logic gates, ensuring that each gate receives the signal at substantially different times, thereby spacing out short circuit currents and reducing the overall current spike without the need for additional capacitors or higher-rated regulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple logic gates are driven simultaneously with the same input signal, then the circuit operates efficiently with minimal delay, but large current spikes occur during logic state transitions
Solution Approach 1:
The drive circuit segments the simultaneous switching event into multiple staggered switching events. Each logic gate receives the input signal at a different time through separate drive circuits with controlled delay differences, dividing the total current spike into smaller sequential spikes that do not overlap
Solution Approach 2:
The drive circuits introduce periodic delay variations to the input signal delivered to each logic gate. By controlling the signal arrival times to be staggered rather than simultaneous, the switching actions are distributed over time periods, converting a single large periodic current spike into multiple smaller distributed spikes
2Reliability
If a decoupling capacitor is added to reduce current spike, then the supply voltage stability improves, but the circuit board space increases
Solution Approach 1:
The invention extracts the need for decoupling capacitors by addressing the root cause of supply voltage instability - simultaneous switching current spikes. By staggering the switching times of logic gates through controlled signal delivery, the harmful current spikes are eliminated at their source, making external decoupling capacitors unnecessary and freeing up circuit board space
3Reliability
If a larger regulator is used to handle current spikes, then the supply voltage drop is reduced, but the device size and cost increase
Solution Approach 1:
The invention extracts and eliminates the need for oversized regulators by preventing the generation of large current spikes in the first place. Through staggered signal delivery to logic gates, the switching currents are distributed over time, allowing a smaller, more compact regulator to suffice without compromising supply voltage stability
4Speed
If the rise/fall time of input signal is reduced, then the logic state transition speed increases, but the short circuit current duration increases
Solution Approach 1:
The invention segments the total short circuit current duration by distributing logic state transitions across different time periods. Even though each individual gate switches quickly with fast rise/fall times, the staggered timing ensures that not all gates are switching simultaneously, effectively segmenting the overall current duration into smaller non-overlapping intervals
Data Source
AI summary
A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display.