Staggered External Electrodes for Multilayer Chip Capacitor ESL Reduction
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Solution Overview
Problem
Conventional multilayer chip capacitors face challenges in reducing equivalent series inductance (ESL) and size while preventing external electrodes on opposing sides from shorting, which hinders the development of smaller capacitors and increases the risk of defects during mounting.
Innovation Solution
The multilayer chip capacitor design features staggered and spaced external electrodes on opposing sides, with internal electrodes extended to connect with external electrodes, reducing the likelihood of shorts and minimizing ESL by altering the current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If external electrodes are applied on broad areas of opposing sides to reduce ESL, then equivalent series inductance is reduced, but external electrodes are more likely to be shorted to each other
Solution Approach 1:
The patent applies asymmetry by staggering the external electrodes such that they are not positioned directly opposite each other. Instead, the external electrodes are arranged at offset positions along the length direction of the capacitor body, creating an asymmetric configuration that prevents direct alignment and potential short circuits while maintaining effective electrical connection for low ESL performance
Solution Approach 2:
The patent resolves the contradiction by transitioning from a one-dimensional opposite-facing electrode arrangement to a two-dimensional staggered arrangement. The external electrodes are positioned at different locations along the length direction, effectively using the longitudinal dimension to space electrodes apart while maintaining their functional connection, thus preventing shorts without increasing ESL
2Volume of moving object
If capacitor size is reduced to allow more capacitors in parallel, then device footprint is reduced, but external electrodes on opposing sides are disposed at shorter distance increasing short risk
Solution Approach 1:
The staggered asymmetric arrangement of external electrodes allows the capacitor to be miniaturized while maintaining adequate spacing between electrodes of opposite polarity. By offsetting electrode positions along the length direction, the design prevents direct opposition and short circuits even when the overall capacitor dimensions are reduced
Solution Approach 2:
The patent utilizes the length direction dimension to stagger electrode positions, effectively distributing electrodes along the longitudinal axis rather than having them directly oppose each other. This dimensional approach allows compact sizing while maintaining safe electrode separation distances
3Ease of manufacture
If external electrodes are extended by process limitations, then manufacturing is simplified, but electrode length increases causing difficulty in mounting and higher short risk
Solution Approach 1:
The patent segments the electrode function by separating the internal electrode extension (which maintains electrical connection) from the external electrode positioning (which determines mounting characteristics). The external electrodes are positioned at staggered locations that provide adequate spacing for mounting while the internal electrodes maintain necessary electrical connections through the capacitor body
Data Source
AI summary
A multilayer chip capacitor including: a capacitor body where a plurality of dielectric layers are deposited, the capacitor body having opposing first and second sides and opposing third and fourth sides; a plurality of layers of internal electrodes deposited alternately with the dielectric layers in the capacitor body; at least one first external electrode formed on the first side; and at least one second external electrode formed on the second side, wherein the first and second external electrodes are staggered with respect to each other and spaced apart from each other at a certain distance in a length direction of the first side.