Staggered Erase Scheduling for Memory Buffer Reduction
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Solution Overview
Problem
In rewritable non-volatile memory modules, simultaneous erase operations across all memory sub-modules lead to a requirement for large buffer memory capacity due to prolonged execution times, hindering continuous data writing from the host system.
Innovation Solution
Implement a data erasing method where only a subset of physical erasing units within a group are used for erase operations at any given time, allowing for staggered execution and reducing the need for large buffer memory by enabling concurrent writing during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all memory sub-modules perform erase operations simultaneously, then parallel write efficiency is maintained, but buffer memory capacity must be large to store incoming data
Solution Approach 1:
The physical erasing units are divided into multiple groups, and erase operations are performed on different groups at different times rather than all simultaneously. This segmentation allows some memory sub-modules to be available for write operations while others perform erase, reducing the buffer memory capacity needed to store incoming data during erase operations.
Solution Approach 2:
The system dynamically adjusts which physical erasing units perform erase operations at any given time, rather than using a fixed simultaneous erase approach. This dynamic scheduling allows the system to balance erase operations with write operations, maintaining parallel write efficiency while reducing buffer requirements.
2Duration of action of moving object
If all memory sub-modules perform erase operations simultaneously, then erase operation completes in parallel, but data from host system must be temporarily stored in buffer memory
Solution Approach 1:
The memory system segments erase operations across different physical erasing unit groups, performing erases in staggered batches rather than all at once. This maintains reasonable parallel execution time while freeing up memory sub-modules to accept write operations, thereby reducing buffer memory requirements.
Solution Approach 2:
The system ensures continuous useful action by allowing write operations to proceed concurrently with erase operations on different memory sub-modules. This continuous operation reduces the need for buffer memory to temporarily store incoming data, as write operations can proceed without interruption.
3Productivity
If erase operation is performed with physical erasing unit group as unit, then parallel write efficiency is kept, but all memory sub-modules are occupied during erase
Solution Approach 1:
Physical erasing units are segmented into multiple groups that can be erased in different batches. This allows the system to maintain parallel write efficiency by keeping some groups available for writes while erasing others, thereby improving adaptability and concurrent write capability.
Solution Approach 2:
Instead of erasing all physical erasing units in a group simultaneously, the system performs partial erase actions on subsets of units while leaving others available for write operations. This partial action approach maintains write capability during erase operations.
Data Source
AI summary
A data erasing method, a memory control circuit unit and a memory storage device are provided. The method includes selecting a first physical erasing unit group from a plurality of physical erasing unit groups, and performing an erase operation to the first physical erasing unit group, wherein the first physical erasing unit group includes a plurality of first physical erasing units, and the number of at least one second physical erasing unit used to perform the erasing operation at the same time point of the plurality of first physical erasing units is different from the number of the plurality of first physical erasing units.