Staggered FET Gate Structure for Dense Nanosheet Stacks
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Solution Overview
Problem
Nanosheet technology faces challenges in scaling down due to interference between devices as they become smaller and closer, and stacking devices complicates the formation of connections to bottom devices and shared gate structures.
Innovation Solution
A microelectronic structure with staggered channels of upper and lower transistors, where a lower dielectric pillar separates the bottom transistors, and bonding and upper dielectric pillars facilitate the formation of shared gates by connecting independent gates between the channels of upper and lower transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If devices are scaled down and placed closer together, then device density is improved, but device interference increases
Solution Approach 1:
The patent transitions from planar device arrangement to three-dimensional stacked configuration. Multiple transistor layers are vertically stacked with staggered channel positions, utilizing the vertical dimension to increase device density while maintaining horizontal separation through offset channel alignment between layers.
Solution Approach 2:
The device structure is segmented into multiple stacked layers with distinct functional regions. Each layer contains transistors with staggered channel positions, and dielectric pillars are segmented to provide isolation at different vertical levels, reducing interference between adjacent devices.
2Quantity of substance
If devices are stacked vertically, then device density is improved, but connection formation to bottom devices becomes difficult
Solution Approach 1:
Contact structures are formed prior to finalizing the stacked device configuration. The contact structures extend through intermediate layers to reach bottom device regions, establishing electrical connections before subsequent processing steps that might obstruct access to lower devices.
Solution Approach 2:
Dielectric pillars serve as intermediary structures that provide both mechanical support and electrical isolation. These pillars are strategically positioned to enable contact structure routing while maintaining proper electrical isolation between stacked devices.
3Quantity of substance
If devices are stacked vertically, then device density is improved, but shared gate formation becomes difficult
Solution Approach 1:
Gate structures are formed in three-dimensional configurations that wrap around nanosheet channels from multiple directions. The gate extends vertically and laterally to encompass channels in different stacked layers, utilizing spatial arrangement to achieve shared control over multiple transistor layers.
Solution Approach 2:
The gate structure is nested to surround the nanosheet channels, with the gate material conformally coating the channel regions. This nested configuration allows a single gate structure to control multiple channels in different vertical layers, simplifying shared gate formation.
Data Source
AI summary
A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors.