Staggered Flash Memory Startup Reduces Peak Current
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Solution Overview
Problem
The startup process of flash memory devices can lead to errors due to power supply voltage fluctuations, causing the VCC voltage to drop below the nominal operating level, resulting in errors during data reading or writing.
Innovation Solution
Implementing a staggered startup process where only a subset of flash memory devices are powered up at a time, with each subset waiting for a distinct delay period before executing the second portion of instructions, thereby managing the power-up process to prevent voltage drops and errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all flash memory devices are powered up simultaneously, then the startup process is faster, but the power supply voltage drops below the nominal operating level causing errors
Solution Approach 1:
The patent divides the flash memory devices into multiple subsets and powers them up in a staggered manner rather than simultaneously. Each subset is activated at different time intervals, which distributes the power demand over time and prevents the supply voltage from dropping below the nominal operating level, thus maintaining reliability while still achieving relatively fast startup
Solution Approach 2:
The patent implements a dynamic startup sequence where the timing and number of devices powered up in each subset can be adjusted based on system conditions. The controller dynamically manages the power-up sequence to optimize between speed and reliability requirements
2Speed
If all flash memory devices are powered up simultaneously, then the system becomes operational faster, but noise levels increase causing errors during data reading or writing
Solution Approach 1:
By segmenting the flash memory devices into multiple subsets with staggered power-up timing, the patent reduces the peak noise generated during startup. Instead of all devices generating noise simultaneously, the noise is distributed across different time intervals, resulting in lower overall noise levels that prevent errors during data reading or writing
Solution Approach 2:
The patent employs periodic action by powerving up subsets of flash memory devices at different time intervals. This periodic staggering of power-up events spreads the noise generation over time, preventing the accumulation of high noise levels that would occur with simultaneous startup, thus ensuring cleaner signal environments for subsequent operations
3Speed
If all flash memory devices are powered up simultaneously, then the system is ready faster, but the peak current demand becomes unmanageable
Solution Approach 1:
The patent segments the flash memory devices into multiple subsets and powers them up sequentially rather than all at once. This segmentation of the power-up process distributes the current demand over time, preventing excessive peak current that would occur with simultaneous startup, while still achieving relatively fast overall power-up by keeping multiple devices in different subsets ready to activate
Solution Approach 2:
The patent implements dynamic power management by adjusting the power-up sequence of different device subsets based on current demand conditions. The controller can dynamically control the timing and number of devices activated in each subset, optimizing the balance between achieving fast operational readiness and maintaining manageable peak current levels within the power supply capabilities
Data Source
AI summary
A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory.