Staggered Gate Pattern Formation via Dual Etching
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in precisely controlling the size and shape of staggered gate patterns, particularly in deep submicron fields, due to small photolithography process windows and rounded corners, which affect device performance and make metal gate filling difficult.
Innovation Solution
A method involving stacked structures with etching barrier layers and multiple photolithography steps to form a staggered gate pattern, allowing for a larger process window and improved control over the gate pattern's shape and size, transitioning from slot-shaped to line/space-shaped trimming patterns for easier implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional double patterning technique is used to form staggered gate patterns, then the gate pattern can be formed, but the photolithography process window becomes very small and corner rounding occurs
Solution Approach 1:
The patent divides the gate pattern formation into multiple etching steps with different etch selectivities. A first etching step forms a preliminary gate pattern, and a second etching step with different selectivity refines the pattern to achieve the final staggered gate structure with precise dimensions and sharp corners, avoiding the limitations of single-step photolithography
Solution Approach 2:
The patent changes the etching parameters by using multiple etching processes with different selectivities. The first etching process uses one set of parameters to form the initial pattern, while the second etching process uses different parameters (different selectivity) to refine the pattern, enabling precise control of gate pattern size and shape that cannot be achieved with conventional single-step photolithography
2Shape
If trimming slots are used in double patterning to form staggered gates, then gaps can be created, but the slots are difficult to implement with photolithography and corners become rounded
Solution Approach 1:
The patent segments the pattern formation into two distinct etching steps. The first step creates the preliminary structure, and the second step with different selectivity creates the final sharp-cornered staggered pattern. This segmentation avoids the need to form difficult-to-etch slot shapes through photolithography, as each step works with simpler geometric forms that are easier to manufacture
Solution Approach 2:
Instead of directly forming the final complex staggered pattern with slots through photolithography (which causes rounding), the patent inverts the approach by first forming a continuous gate pattern and then selectively removing portions through a second etching step. This reverse approach enables sharp corner formation and precise shape control that cannot be achieved by direct slot formation
3Manufacturing precision
If conventional double patterning is used, then staggered gate pattern can be formed, but precision control of gate size and shape is poor
Solution Approach 1:
The patent achieves precise dimensional control by changing etching parameters between steps. The first etching step uses parameters optimized for forming the preliminary pattern, while the second etching step uses parameters with different selectivity to precisely define the final gate dimensions. This parameter variation enables accurate control of gate pattern size and shape that cannot be achieved with conventional single-step methods
Solution Approach 2:
The patent performs preliminary pattern formation through the first etching step, creating a preliminary gate structure that serves as the basis for the final pattern. This preliminary action allows subsequent refinement with precise dimensional control in the second etching step, achieving high manufacturing precision while systematically managing the additional processing time required
Data Source
AI summary
This disclosure is directed to a method of forming a gate pattern and a semiconductor device. The method comprises: providing a plurality of stacked structures which are parallel to each other and extend continuously in a first direction, and which are composed of a gate material bar and an etching barrier bar thereon; leaving second resist regions between gaps to be formed adjacent to each other across gate bars by a second photolithography process; selectively removing the etching barrier bars by a second etching process; forming a third resist layer having a plurality of openings parallel to each other and extending continuously in a second direction substantially perpendicular to the first direction by a third photolithography process; and forming the gate pattern by a third etching process. The method is capable of having a larger photolithography process window and better controlling the shape and size of a gate pattern.