Staggered Semiconductor Layout for Precise LED Die Transfer
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Solution Overview
Problem
The challenge lies in precisely placing millions of light-emitting diode (LED) chips on a display panel with high area utilization efficiency and yield, particularly due to the need for fast and reliable die transfer technology as LED die sizes decrease and applications expand beyond traditional lighting.
Innovation Solution
A semiconductor device arrangement featuring a substrate with semiconductor devices arranged in a staggered pattern, where the minimum distance between adjacent devices is between 3 μm and 25 μm, allowing for efficient non-contact laser transfer processes that improve alignment tolerance and area utilization by ensuring sufficient space for gas discharge and accurate irradiation during the transfer process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If LED die size is reduced to increase brightness and enable direct display pixel applications, then area utilization efficiency is improved, but manufacturing precision and placement accuracy become more difficult to achieve
Solution Approach 1:
The patent segments the substrate surface into multiple transfer regions with staggered LED die arrangements. This segmentation allows different regions to be processed and transferred independently, improving overall placement accuracy while maintaining high area utilization through efficient space coverage.
Solution Approach 2:
The patent introduces a vertical dimension to the staggered arrangement of LED dies on the substrate. By stacking dies in multiple layers at different heights, the system achieves three-dimensional packaging that dramatically improves area utilization while the staggered positioning in the vertical dimension maintains placement accuracy.
2Productivity
If millions of LED chips are placed on a display panel to increase pixel density, then productivity is improved, but the complexity of die transfer technology increases
Solution Approach 1:
The patent divides the large-scale LED array into multiple smaller transfer regions arranged in a staggered pattern. Each region can be transferred independently using standardized processes, which simplifies the overall transfer technology while achieving high pixel density through the cumulative effect of multiple regions.
Solution Approach 2:
The patent combines multiple transfer regions with staggered arrangements into a single integrated display panel structure. This merging approach achieves high pixel density while using conventional transfer technologies for each individual region, thereby managing complexity.
3Area of moving object
If LED dies are arranged in a staggered pattern with minimum distance of 3-25 μm to improve area utilization, then area utilization efficiency is improved, but the difficulty of detecting and measuring increases
Solution Approach 1:
The staggered arrangement creates measurable vertical height differences between LED dies in adjacent regions. This vertical dimension provides an additional measurement parameter that facilitates detection and alignment while maintaining minimal horizontal spacing for high area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the area utilization efficiency of the substrate, improves the accuracy of LED chip placement, and facilitates efficient transfer processes, enabling the production of high-yield semiconductor devices for next-generation displays.
Implementation Method 1
allowing for efficient non-contact laser transfer processes
Data Source
AI summary
An embodiment of the present disclosure provides a semiconductor device arrangement. This semiconductor device arrangement includes a substrate and a plurality of semiconductor devices. The substrate includes an upper surface. The plurality of semiconductor devices is separately and staggered located on the upper surface, and includes a first semiconductor device and a second semiconductor device. Wherein the first semiconductor device includes a first interior angle, the second semiconductor device includes a second interior angle, and there is a minimum distance between the first interior angle and the second interior angle among the plurality of semiconductor devices, wherein the minimum distance is between 3 μm 25 μm.